How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System von Asiatici, Mikhail, Maiorano, Damian, Ienne, Paolo

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Virtualized Execution Runtime for FPGA Accelerators in the Cloud von Asiatici, Mikhail, George, Nithin, Vipin, Kizheppatt, Fahmy, Suhaib A., Ienne, Paolo

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Introduction to the Special Section on FPGA 2022 von Ienne, Paolo

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Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design von Verma, A.K., Brisk, P., Ienne, P.

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Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT von Soeken, Mathias, Mishchenko, Alan, Petkovska, Ana, Sterin, Baruch, Ienne, Paolo, Brayton, Robert K., De Micheli, Giovanni

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Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips von Guerrieri, Andrea, Kashani-Akhavan, Sahand, Asiatici, Mikhail, Ienne, Paolo

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Introduction of Architecturally Visible Storage in Instruction Set Extensions von Biswas, P., Dutt, N.D., Pozzi, L., Ienne, P.

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From C/C++ Code to High-Performance Dataflow Circuits von Josipovic, Lana, Guerrieri, Andrea, Ienne, Paolo

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A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions von Regazzoni, Francesco, Cevrero, Alessandro, Standaert, François-Xavier, Badel, Stephane, Kluter, Theo, Brisk, Philip, Leblebici, Yusuf, Ienne, Paolo

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Design Space Exploration of LDPC Decoders Using High-Level Synthesis von Andrade, Joao, George, Nithin, Karras, Kimon, Novo, David, Pratas, Frederico, Sousa, Leonel, Ienne, Paolo, Falcao, Gabriel, Silva, Vitor

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Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs von Asiatici, Mikhail, Ienne, Paolo

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Advanced Parallel Processing Technologies: 11th International Symposium, APPT 2015, Jinan, China, August 20-21, 2015, Proceedings von Chen, Yunji, Ienne, Paolo, Ji, Qing

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Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity Patterns von Nikolić, Stefan, Ienne, Paolo

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Software controlled cell bit-density to improve NAND flash lifetime von Jimenez, Xavier, Novo, David, Ienne, Paolo

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An Out-of-Order Load-Store Queue for Spatial Computing von Josipovic, Lana, Brisk, Philip, Ienne, Paolo

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An EDA-friendly protection scheme against side-channel attacks von Bayrak, Ali Galip, Velickovic, Nikola, Regazzoni, Francesco, Novo, David, Brisk, Philip, Ienne, Paolo

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DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis von Cheng, Jianyi, Josipovic, Lana, Constantinides, George A., Ienne, Paolo, Wickerson, John

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Manycore clique enumeration with fast set intersections von Blanuša, Jovan, Stoica, Radu, Ienne, Paolo, Atasu, Kubilay

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Resource Sharing in Dataflow Circuits von Josipović, Lana, Marmet, Axel, Guerrieri, Andrea, Ienne, Paolo

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Detailed Placement for Dedicated LUT-Level FPGA Interconnect von Nikolić, Stefan, Zgheib, Grace, Ienne, Paolo

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