FPGA-based Garbling Accelerator with Parallel Pipeline Processing von OISHI, Rin, KADOMOTO, Junichiro, IRIE, Hidetsugu, SAKAI, Shuichi

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Toward Wirelessly Cooperated Shape-Changing Computing Particles von Kadomoto, Junichiro, Sasatani, Takuya, Narumi, Koya, Usami, Naoto, Irie, Hidetsugu, Sakai, Shuichi, Kawahara, Yoshihiro

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A Principal Factor of Performance in Decoupled Front-End von DEGAWA, Yuya, KOIZUMI, Toru, NAKAMURA, Tomoki, SHIOYA, Ryota, KADOMOTO, Junichiro, IRIE, Hidetsugu, SAKAI, Shuichi

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Design and Evaluation of a Configurable Query Processing Hardware for Data Streams von OGE, Yasin, YOSHIMI, Masato, MIYOSHI, Takefumi, KAWASHIMA, Hideyuki, IRIE, Hidetsugu, YOSHINAGA, Tsutomu

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Flexible Approximate Computing for Mitigating Branch Divergence in GPUs von Matsuo, Reoma, Degawa, Yuya, Irie, Hidetsugu, Sakai, Shuichi, Shioya, Ryota

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Using Cacheline Reuse Characteristics for Prefetcher Throttling von IRIE, Hidetsugu, MIYOSHI, Takefumi, HONJO, Goki, HIRAKI, Kei, YOSHINAGA, Tsutomu

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Computation-Communication Overlap of Linpack on a GPU-Accelerated PC Cluster von OHMURA, Junichi, MIYOSHI, Takefumi, IRIE, Hidetsugu, YOSHINAGA, Tsutomu

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TURBULENCE: Complexity-Effective Out-of-Order Execution on GPU With Distance-Based ISA von Matsuo, Reoma, Koizumi, Toru, Irie, Hidetsugu, Sakai, Shuichi, Shioya, Ryota

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Cycle-Oriented Dynamic Approximation: Architectural Framework to Meet Performance Requirements von Degawa, Yuya, Suzuki, Shota, Kadomoto, Junichiro, Irie, Hidetsugu, Sakai, Shuichi

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A Fully Optical Ring Network-on-Chip with Static and Dynamic Wavelength Allocation von CISSE, Ahmadou Dit Adi, KOIBUCHI, Michihiro, YOSHIMI, Masato, IRIE, Hidetsugu, YOSHINAGA, Tsutomu

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Ultra Dependable Processor von SAKAI, Shuichi, GOSHIMA, Masahiro, IRIE, Hidetsugu

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A Fully Optical Ring Network-on-Chip with Static and Dynamic Wavelength Allocation von Cisse, Ahmadou Dit Adi, Koibuchi, Michihiro, Yoshimi, Masato, Irie, Hidetsugu, Yoshinaga, Tsutomu

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An Efficient Path Setup for a Hybrid Photonic Network-on-Chip von ADI, Cisse Ahmadou Dit, Matsutani, Hiroki, Koibuchi, Michihiro, Irie, Hidetsugu, Miyoshi, Takefumi, Yoshinaga, Tsutomu

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Using Cacheline Reuse Characteristics for Prefetcher Throttling : Parallel and Distributed Computing and Networking von IRIE, Hidetsugu, MIYOSHI, Takefumi, HONJO, Goki, HIRAKI, Kei, YOSHINAGA, Tsutomu

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Using Cacheline Reuse Characteristics for Prefetcher Throttling von IRIE, Hidetsugu, MIYOSHI, Takefumi, HONJO, Goki, HIRAKI, Kei, YOSHINAGA, Tsutomu

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A Fully Optical Ring Network-on-Chip with Static and Dynamic Wavelength Allocation : Parallel and Distributed Computing and Networking von CISSE, Ahmadou Dit Adi, KOIBUCHI, Michihiro, YOSHIMI, Masato, IRIE, Hidetsugu, YOSHINAGA, Tsutomu

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Computation-Communication Overlap of Linpack on a GPU-Accelerated PC Cluster : Parallel and Distributed Computing and Networking von OHMURA, Junichi, MIYOSHI, Takefumi, IRIE, Hidetsugu, YOSHINAGA, Tsutomu

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Parallel Numerical Simulation of Visual Neurons for Analysis of Optical Illusion von Egashira, A., Satoh, S., Irie, H., Yoshinaga, T.

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Ultra Dependable Processor : Advanced processors based on novel concepts in computation von SAKAI, Shuichi, GOSHIMA, Masahiro, IRIE, Hidetsugu

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CCCPO: Robust Prefetcher Optimization Technique Based on Cache Convection von Irie, H., Miyoshi, T., Honjo, G., Hiraki, K., Yoshinaga, T.

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