Silicon Device Scaling to the Sub-10-nm Regime von Ieong, Meikei, Doris, Bruce, Kedzierski, Jakub, Rim, Ken, Yang, Min

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Hybrid-orientation technology (HOT): opportunities and challenges von Min Yang, Chan, V.W.C., Chan, K.K., Shi, L., Fried, D.M., Stathis, J.H., Chou, A.I., Gusev, E., Ott, J.A., Burns, L.E., Fischetti, M.V., Meikei Ieong

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CMOS circuit performance enhancement by surface orientation optimization von Chang, L., Leong, M., Yang, M.

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Transistor-and Circuit-Design Optimization for Low-Power CMOS von Mi-Chang Chang, Chih-Sheng Chang, Chih-Ping Chao, Ken-Ichi Goto, Meikei Ieong, Lee-Chung Lu, Diaz, C.H.

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Extension and source/drain design for high-performance FinFET devices von Kedzierski, J., Meikei Ieong, Nowak, E., Kanarsky, T.S., Ying Zhang, Roy, R., Boyd, D., Fried, D., Wong, H.-S.P.

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Self-aligned n-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate von Huiling Shang, Kam-Leung Lee, Kozlowski, P., D'Emic, C., Babich, I., Sikorski, E., Meikei Ieong, Wong, H.-S.P., Guarini, K., Haensch, W.

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Foreword Special Issue on Advanced Technology for Ultra-Low Power Electronic Devices von Berger, Paul R., Chin, Albert, Nishiyama, Akira, Ieong, Meikei

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Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO2 gate dielectrics von Min Yang, Gusev, E.P., Meikei Ieong, Gluschenkov, O., Boyd, D.C., Chan, K.K., Kozlowski, P.M., D'Emic, C.P., Sicina, R.M., Jamison, P.C., Chou, A.I.

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Threshold voltage control in NiSi-gated MOSFETs through SIIS von Kedzierski, J., Boyd, D., Cabral, C., Ronsheim, P., Zafar, S., Kozlowski, P.M., Ott, J.A., Meikei Ieong

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Fabrication of metal gated FinFETs through complete gate silicidation with Ni von Kedzierski, J., Meikei Ieong, Kanarsky, T., Ying Zhang, Wong, H.-S.P.

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Threshold voltage control in NiSi-gated MOSFETs through SIIS von Kedzierski, J, Boyd, D, Cabral, C., Jr, Ronsheim, P, Zafar, S, Kozlowski, P.M, Ott, J.A, Meikei Ieong, Meikei Ieong

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Strain for CMOS performance improvement von Chan, V., Ken Rim, Meikei Ieong, Sam Yang, Rajeev Malik, Young Way Teh, Min Yang, Qiqing

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FinFET design considerations based on 3-D simulation and analytical modeling von Pei, G., Kedzierski, J., Oldiges, P., Ieong, M., Kan, E.C.-C.

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Past, present, and future von Ieong, Meikei

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Influence of hydrodynamic models on the prediction of submicrometer device characteristics von Ieong, Mei Kei, Tang, Ting-wei

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Transistor scaling with novel materials von Ieong, Meikei, Narayanan, Vijay, Singh, Dinkar, Topol, Anna, Chan, Victor, Ren, Zhibin

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Investigation of CMOS devices with embedded SiGe source/drain on hybrid orientation substrates von Qiqing Ouyang, Min Yang, Holt, J., Panda, S., Huajie Chen, Utomo, H., Fischetti, M., Rovedo, N., Jinghong Li, Klymko, N., Wildman, H., Kanarsky, T., Costrini, G., Fried, D.M., Bryant, A., Ott, J.A., Meikei Ieong, Chun-Yung Sung

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Nano-CMOS scaling: Novel devices and materials von Meikei Ieong

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Mobility and CMOS devices/circuits on sub-10nm [110] ultra thin body SOI von Huiling Shang, Rubino, J., Doris, B., Topol, A., Sleight, J., Cai, J., Chang, L., Ott, A., Kedzierski, J., Chan, K., Shi, L., Babich, K., Newbury, J., Sikorski, E., To, B.N., Zhang, Y., Guarini, K.W., Meikei Ieong

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Carbon Implanted Halo for Super Halo Characteristic NFETs in Bulk and SOI von Ellis-Monaghan, J., Kam-Leung Lee, Meikei Ieong, Yang, I.

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