High-Speed Architectures for Multiplication Using Reordered Normal Basis von Hosseinzadeh Namin, Ashkan H., Huapeng Wu, Ahmadi, M.

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A Word-Level Finite Field Multiplier Using Normal Basis von Namin, Ashkan Hosseinzadeh, Huapeng Wu, Ahmadi, Majid

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A High-Speed Word Level Finite Field Multiplier in F2m Using Redundant Representation von HOSSEINZADEH NAMIN, Ashkan, HUAPENG WU, AHMADI, Majid

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An Efficient Finite Field Multiplier Using Redundant Representation von Namin, Ashkan Hosseinzadeh, Wu, Huapeng, Ahmadi, Majid

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A New Finite-Field Multiplier Using Redundant Representation von Namin, A.H., Huapeng Wu, Ahmadi, M.

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Block Recombination Approach for Subquadratic Space Complexity Binary Field Multiplication Based on Toeplitz Matrix-Vector Product von Hasan, M. Anwar, Meloni, Nicolas, Namin, Ashkan H., Negre, Christophe

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Improved Area-Time Trade-offs for Field Multiplication using Optimal Normal Bases von Adikari, Jithra, Barsoum, Ayad, Hasan, Anwar, Namin, Ashkan Hosseinzadeh, Negre, Christophe

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Toeplitz Matrix Approach for Binary Field Multiplication Using Quadrinomials von Hasan, M. A., Namin, A. H., Negre, C.

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Efficient hardware implementation of the hyperbolic tangent sigmoid function von Namin, A.H., Leboeuf, K., Muscedere, R., Huapeng Wu, Ahmadi, M.

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METHOD AND APPARATUS TO MIGRATE MORE SENSITIVE WORKLOADS TO FASTER CHIPLETS von Hosseinzadeh Namin, Ashkan, Jain, Ashish

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Comb Architectures for Finite Field Multiplication in F(2^m) von Namin, A.H., Huapeng Wu, Ahmadi, M.

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Graphics processing units with power management and latency reduction von Hosseinzadeh Namin, Ashkan, Jin, Seunghun, Tan, Teik-Chung, Godey, Sreekanth

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WORKLOAD-BASED CLOCK ADJUSTMENT AT A PROCESSING UNIT von REGNIERE, Louis, NIJASURE, Mangesh P, HOSSEINZADEH NAMIN, Ashkan, MANTOR, Michael

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A high speed word level finite field multiplier using reordered normal basis von Namin, Ashkan Hosseinzadeh, Huapeng Wu, Ahmadi, Majid

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Reducing save restore latency for power control based on write signals von Hosseinzadeh Namin, Ashkan, Acharya, Anirudh R, Ashkar, Alexander Fuad

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WORKLOAD-BASED CLOCK ADJUSTMENT AT A PROCESSING UNIT von REGNIERE, Louis, NIJASURE, Mangesh P, HOSSEINZADEH NAMIN, Ashkan, MANTOR, Michael

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GRAPHICS PROCESSING UNITS WITH POWER MANAGEMENT AND LATENCY REDUCTION von TAN, Teik-Chung, HOSSEINZADEH NAMIN, Ashkan, JIN, Seunghun, GODEY, Sreekanth

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Efficient VLSI implementation of a finite field multiplier using reordered normal basis von Leboeuf, K, Namin, A H, Huapeng Wu, Muscedere, R, Ahmadi, M

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Workload-based clock adjustment at a processing unit von Hosseinzadeh Namin, Ashkan, Mantor, Michael, Regniere, Louis, Nijasure, Mangesh P

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REDUCING SAVE RESTORE LATENCY FOR POWER CONTROL von ASHKAR, Alexander Fuad, HOSSEINZADEH NAMIN, Ashkan, ACHARYA, Anirudh R

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