A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems von Kennedy, J., Mooney, R., Ellis, R., Jaussi, J., Borkar, S., Jung-Hwan Choi, Jae-Kwan Kim, Chan-Kyong Kim, Woo-Seop Kim, Chang-Hyun Kim, Soo-In Cho, Loeffler, S., Hoffmann, J., Hokenmaier, W., Houghton, R., Vogelsang, T.

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Co-design of a novel CMOS highly parallel, low-power, multi-chip neural network accelerator von Hokenmaier, W, Jurasek, R, Bowen, E, Granger, R, Odom, D

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A 2Gb/s point-to-point heterogeneous voltage capable DRAM interface for capacity-scalable memory subsystems von Kennedy, J., Ellis, R., Jaussi, J., Mooney, R., Borkar, S., Jung-Hwan Choi, Jae-Kwan Kim, Chan-Kyong Kim, Woo-Seop Kim, Chang-Hyun Kim, Soo-In Cho, Loeffler, S., Hoffmann, J., Hokenmaier, W., Houghton, R., Vogelsang, T.

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A 90nm 512Kb embedded Phase-Change Memory macro with fast read access time for digital multimedia broadcasting applications von Hongwei Hong, Chien Wang, Ruizhe Wang, Sam Sheng, Zhongling Zhou, Hwang, C., Scoville, C., Labrecque, D., Jurasek, R., Butler, V., Hokenmaier, W.

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Dynamic random-access memory with embedded artificial neural network functionality von Jurasek, Ryan A, Hokenmaier, Wolfgang, Labrecque, Donald W

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Content addressable dynamic random-access memory with parallel search functionality von Hokenmaier Wolfgang, Willey Aaron D, Labrecque Donald W, Jurasek Ryan A

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