Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor von Warnock, J., Wendel, D., Aipperspach, T., Behnen, E., Cordes, R.A., Dhong, S.H., Hirairi, K., Murakami, H., Onishi, S., Pham, D.C., Pille, J., Posluszny, S.D., Takahashi, O., Huajun Wen

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Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: V-Aware Dual Supply Voltage Technique von Fuketa, H., Hirairi, K., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H., Sakurai, T.

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13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital L... von Hirairi, K., Okuma, Y., Fuketa, H., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H., Sakurai, T.

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Misleading energy and performance claims in sub/near threshold digital systems von Yu Pu, Xin Zhang, Huang, Jim, Muramatsu, Atsushi, Nomura, Masahiro, Hirairi, K, Takata, H, Sakurabayashi, T, Miyano, Shinji, Takamiya, M, Sakurai, T

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Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS von Yasufuku, T., Iida, S., Fuketa, H., Hirairi, K., Nomura, M., Takamiya, M., Sakurai, T.

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0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS von Nomura, M., Muramatsu, A., Takeno, H., Hattori, S., Ogawa, D., Nasu, M., Hirairi, K., Kumashiro, S., Moriwaki, S., Yamamoto, Y., Miyano, S., Hiraku, Y., Hayashi, I., Yoshioka, K., Shikata, A., Ishikuro, H., Ahn, M., Okuma, Y., Zhang, X., Ryu, Y., Ishida, K., Takamiya, M., Kuroda, T., Shinohara, H., Sakurai, T.

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The circuits and physical design of the synergistic processor element of a CELL processor von Takahashi, O., Cook, R., Cottier, S., Dhong, S.H., Flachs, B., Hirairi, K., Kawasumi, A., Murakami, H., Noro, H., Oh, H., Onishi, S., Pille, J., Silberman, J., Yong, S.

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The circuit design of the synergistic processor element of a CELL processor von Takahashi, O., Cook, R., Cottier, S., Dhong, S.H., Flachs, B., Hirairi, K., Kawasumi, A., Murakami, H., Noro, H., Oh, H., Onish, S., Pille, J., Silberman, J.

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A dynamic logic circuit embedded flip-flop for ASIC design von Hirairi, K., Kosaka, H., Moriki, K., Keino, K., Onuma, K.

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The circuit design of the synergistic processor element of a CELL processor von Takahashi, O., Cook, R., Cottier, S., Dhong, S. H., Flachs, B., Hirairi, K., Kawasumi, A., Murakami, H., Noro, H., Oh, H., Onish, S., Pille, J., Silberman, J.

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24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits von Yasufuku, T., Hirairi, K., Yu Pu, Yun Fei Zheng, Takahashi, R., Sasaki, M., Fuketa, H., Muramatsu, A., Nomura, M., Shinohara, H., Takamiya, M., Sakurai, T.

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0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS von Nomura, M., Muramatsu, A., Takeno, H., Hattori, S., Ogawa, D., Nasu, M., Hirairi, K., Kumashiro, S., Moriwaki, S., Yamamoto, Y., Miyano, S., Hiraku, Y., Hayashi, I., Yoshioka, K., Shikata, A., Ishikuro, H., Ahn, M., Okuma, Y., Zhang, X., Ryu, Y., Ishida, K., Takamiya, M., Kuroda, T., Shinohara, H., Sakurai, T.

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The Power Conscious Synergistic Processor Element of a Cell Processor von Takahashi, O., Cottier, S., Dhong, S.H., Flachs, B., Hirairi, K., Peter Hofstee, H., Michael, B., Noro, H., Wendel, D., White, M.

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