Processing Technologies for Advanced Ge Devices von Loo, R., Hikavyy, A. Y., Witters, L., Schulze, A., Arimura, H., Cott, D., Mitard, J., Porret, C., Mertens, H., Ryan, P., Wall, J., Matney, K., Wormington, M., Favia, P., Richard, O., Bender, H., Thean, A., Horiguchi, N., Mocuta, D., Collaert, N.

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(Invited) Very Low Temperature Epitaxy of Group-IV Semiconductors for Use in FinFET, Stacked Nanowires and Monolithic 3D Integration von Porret, Clement, Hikavyy, Andriy Yakovitch, Gomez Granados, Juan Fernando, Baudot, Sylvain, Vohra, Anurag, Kunert, Bernardette, Douhard, Bastien, Bogdanowicz, Janusz, Schaekers, Marc, Kohen, David, Margetis, Joe, Tolle, John, Lima, Lucas, Sammak, Amir, Scappucci, Giordano, Rosseel, Erik, Langer, Robert, Loo, Roger

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(Invited) Processing Technologies for Advanced Ge Devices von Loo, Roger, Hikavyy, Andriy Yakovitch, Witters, Liesbeth, Schulze, Andreas, Arimura, Hiroaki, Cott, Daire, Mitard, Jerome, Porret, Clement, Mertens, Hans, Ryan, Paul, Wall, John, Matney, Kevin, Wormington, Matthew, Favia, Paola, Richard, Olivier, Bender, Hugo, Horiguchi, Naoto, Collaert, Nadine, Thean, Aaron

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Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails von Veloso, A., Jourdain, A., Radisic, D., Chen, R., Arutchelvan, G., O'Sullivan, B., Arimura, H., Stucchi, M., De Keersgieter, A., Hosseini, M., Hopf, T., D'have, K., Wang, S., Dupuy, E., Mannaert, G., Vandersmissen, K., Iacovo, S., Marien, P., Choudhury, S., Schleicher, F., Sebaai, F., Oniki, Y., Zhou, X., Gupta, A., Schram, T., Briggs, B., Lorant, C., Rosseel, E., Hikavyy, A., Loo, R., Geypen, J., Batuk, D., Martinez, G. T., Soulie, J. P., Devriendt, K., Chan, B. T., Demuynck, S., Hiblot, G., Van der Plas, G., Ryckaert, J., Beyer, G., Litta, E. Dentoni, Beyne, E., Horiguchi, N.

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3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability von Vandooren, A., Franco, J., Parvais, B., Wu, Z., Witters, L., Walke, A., Li, W., Peng, L., Deshpande, V., Bufler, F. M., Rassoul, N., Hellings, G., Jamieson, G., Inoue, F., Verbinnen, G., Devriendt, K., Teugels, L., Heylen, N., Vecchio, E., Zheng, T., Rosseel, E., Vanherle, W., Hikavyy, A., Chan, B. T., Ritzenthaler, R., Besnard, G., Schwarzenbach, W., Gaudin, G., Radu, I., Nguyen, B.-Y., Waldron, N., De Heyn, V., Mocuta, D., Collaert, N.

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(Invited) Selective Epitaxial Growth of High-P Si:P for Source/Drain Formation in Advanced Si nFETs von Rosseel, Erik, Dhayalan, Sathish Kumar, Hikavyy, Andriy Yakovitch, Loo, Roger, Profijt, Harald Benjamin, Kohen, David, Kubicek, Stefan, Chiarella, Thomas, Yu, Hao, Horiguchi, Naoto, Mocuta, Dan, Barla, Kathy, Thean, Aaron, Bartlett, Gregory, Margetis, Joe, Bhargava, Nupur, Tolle, John

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Ge-Source Vertical Tunnel FETs Using a Novel Replacement-Source Integration Scheme von Rooyackers, Rita, Vandooren, Anne, Verhulst, Anne S., Walke, Amey Mahadev, Simoen, Eddy, Devriendt, Katia, Lo-Corotondo, Sabrina, Demand, Marc, Bryce, George, Loo, Roger, Hikavyy, Andriy, Vandeweyer, Tom, Huyghebaert, Cedric, Collaert, Nadine, Thean, Aaron V. Y.

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(Invited) Gate-All-Around Transistors Based on Vertically Stacked Si Nanowires von Mertens, Hans, Ritzenthaler, Romain, Hikavyy, Andriy Yakovitch, Kim, Min-Soo, Tao, Zheng, Wostyn, Kurt, Schram, Tom, Kunnen, Eddy, Ragnarsson, Lars-Åke, Dekkers, Harold F. W., Hopf, Toby, Devriendt, Katia, Tsvetanova, Diana, Chew, Soon Aik, Kikuchi, Yoshiaki, Van Besien, Els, Rosseel, Erik, Mannaert, Geert, De Keersgieter, An, Chasin, Adrian, Kubicek, Stefan, Dangol, Anish, Demuynck, Steven, Barla, Kathy, Mocuta, Dan, Horiguchi, Naoto

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(Invited) Stress Techniques in Advanced Transistor Architectures: Bulk FinFETs and Implant-Free Quantum Well Transistors von Eneman, Geert, Witters, Liesbeth, Collaert, Nadine, Mitard, Jerome, Hellings, Geert, Yamaguchi, Shinpei, De Keersgieter, An, Hikavyy, Andriy, Vincent, Benjamin, Favia, Paola, Bender, Hugo, Veloso, Anabela, Chiarella, Thomas, Togo, Mitsuhiro, Loo, Roger, De Meyer, Kristin, Mercha, Abdelkarim, Horiguchi, Naoto, Thean, Aaron

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(Invited) Stress Simulations of Si- and Ge-Channel FinFETs for the 14 nm-Node and Beyond von Eneman, Geert, Brunco, David P., Witters, Liesbeth, Vincent, Benjamin, Favia, Paola, Hikavyy, Andriy, De Keersgieter, An, Mitard, Jerome, Loo, Roger, Veloso, Anabela, Richard, Olivier, Bender, Hugo, Vandervorst, Wilfried, Caymax, Matty, Horiguchi, Naoto, Collaert, Nadine, Thean, Aaron

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Selective Epitaxial Growth: Trends in a Modern Transistor Device Fabrication von Hikavyy, Andriy Y., Vanherle, Wendy, Dekoster, Johan, Witters, Liesbeth, Hoffmann, Thomas, Loo, Roger

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Stress analysis of Si1-xGex embedded source/drain junctions von BARGALLO GONZALEZ, M, SIMOEN, E, TOMASINI, P, THOMAS, S. G, LU, J. P, WISE, R, NAKA, N, OKUNO, Y, ENEMAN, G, HIKAVYY, A, VERHEYEN, P, LOO, R, CLAEYS, C, MACHKAOUTSAN, V

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Growth and Processing Defects in CMOS Homo- and Hetero-Epitaxy von Simoen, Eddy, Bargallo Gonzalez, Mireia, Eneman, Geert, Rosseel, Eric, Hikavyy, Andriy Y., Kobayashi, D., Loo, Roger, Caymax, Matty, Claeys, Cor

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Application Of HCl Gas Phase Etch In The Production Of Novel Devices von Hikavyy, Andriy Y., Rooyackers, Rita, Verheyen, Peter, Leys, Frederik, Vellianitis, Georgios, Van Dal, Mark J., Lander, Rob, Loo, Roger

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Material Aspects and Challenges for SOI FinFET Integration von Van Dal, Mark J., Vellianitis, Georgios, Duffy, Ray, Doornbos, Gerben, Pawlak, Bartek, Duriez, Blandine, Lai, Lhi-Shue, Hikavyy, Andriy Y., Vandeweyer, Tom, Demand, Marc, Altamirano, Efrain, Rooyackers, Rita, Witters, Liesbeth, Collaert, Nadine, Jurczak, Malgorzata, Kaiser, Monja, Weemaes, Robbert G., Lander, Rob

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SiCP Selective Epitaxial Growth in Recessed Source/Drain Regions yielding to Drive Current Enhancement in n-channel MOSFET von Bauer, Matthias, Machkaoutsan, Vladimir, Zhang, Yangting, Weeks, Doran, Spear, Jennifer, Thomas, Shawn, Verheyen, Peter, Kerner, C., Clemente, F., Bender, Hugo, Shamiryan, D., Loo, Roger, Hikavyy, A., Hoffmann, T., Absil, Philipe, Biesemans, Serge

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Stress analysis of Si sub(1-) sub(x)Ge sub(x embedded source/drain junctions) von Gonzalez, MBargallo, Simoen, E, Naka, N, Okuno, Y, Eneman, G, Hikavyy, A, Verheyen, P, Loo, R, Claeys, C, Machkaoutsan, V, Tomasini, P, Thomas, S G, Lu, J P, Wise, R

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Stress analysis of Si 1− x Ge x embedded source/drain junctions von Bargallo Gonzalez, M., Simoen, E., Naka, N., Okuno, Y., Eneman, G., Hikavyy, A., Verheyen, P., Loo, R., Claeys, C., Machkaoutsan, V., Tomasini, P., Thomas, S.G., Lu, J.P., Wise, R.

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8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS von Witters, L, Takeoka, S, Yamaguchi, S, Hikavyy, A, Shamiryan, D, Cho, M, Chiarella, T, Ragnarsson, L.-A, Loo, R, Kerner, C, Crabbe, Y, Franco, J, Tseng, J, Wang, W E, Rohr, E, Schram, T, Richard, O, Bender, H, Biesemans, S, Absil, P, Hoffmann, T

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Study of electrically active defects in epitaxial layers on silicon von Simoen, Eddy, Dhayalan, SK, Jayachandran, S, Gupta, S, Gencarelli, F, Hikavyy, A, Loo, R, Rosseel, E, Delabie, A, Caymax, M, Langer, R, Barla, K, Vrielinck, Henk, Lauwaert, Johan

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