A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance von Bailey, Steven, Rigge, Paul, Han, Jaeduk, Lin, Richard, Chang, Eric Y., Mao, Howard, Wang, Zhongkai, Markley, Chick, Izraelevitz, Adam M., Wang, Angie, Narevsky, Nathan, Bae, Woorham, Shauck, Steve, Montano, Sergio, Norsworthy, Justin, Razzaque, Munir, Ma, Wen Hau, Lentiro, Akalu, Doerflein, Matthew, Heckendorn, Darin, McGrath, Jim, DeSeta, Franco, Shoham, Ronen, Stellfox, Mike, Snowden, Mark, Cole, Joseph, Fuhrman, Daniel R., Richards, Brian, Bachrach, Jonathan, Alon, Elad, Nikolic, Borivoje

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