A 0.5 V 10 b 3 MS/s 2-Then-1b/Cycle SAR ADC With Digital-Based Time-Domain Reference and Dual-Mode Comparator von Jung, Dong-Kyu, Seong, Kiho, Han, Jae-Soub, Shim, Yong, Baek, Kwang-Hyun

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Time-Interleaved SAR ADC with Background Timing-Skew Calibration for UWB Wireless Communication in IoT Systems von Seong, Kiho, Jung, Dong-Kyu, Yoon, Dong-Hyun, Han, Jae-Soub, Kim, Ju-Eon, Kim, Tony Tae-Hyoung, Lee, Woojoo, Baek, Kwang-Hyun

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A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator von Han, Jae-Soub, Eom, Tae-Hyeok, Choi, Seong-Wook, Seong, Kiho, Yoon, Dong-Hyun, Kim, Tony Tae-Hyong, Baek, Kwang-Hyun, Shim, Yong

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A 2.5 GS/s 7-Bit 5-Way Time-Interleaved SAR ADC With On-Chip Background Offset and Timing-Skew Calibration von Seong, Kiho, Han, Jae-Soub, Shim, Yong, Baek, Kwang-Hyun

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Design and Analysis of Low Power and High SFDR Direct Digital Frequency Synthesizer von Choi, Ji-Min, Yoon, Dong-Hyun, Jung, Dong-Kyu, Seong, Kiho, Han, Jae-Soub, Lee, Woojoo, Baek, Kwang-Hyun

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Highly efficient and wide input range maximum power point tracking circuit with coarse and fine stages for energy harvesting systems von Dang, Van‐Thai, Han, Jae‐Soub, Shim, Yong, Baek, Kwang‐Hyun

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A 3.2-GHz 178-fsrms Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier von Yoon, Dong-Hyun, Jung, Dong-Kyu, Seong, Kiho, Han, Jae-Soub, Chung, Keun-Yong, Kim, Ju-Eon, Kim, Tony Tae-Hyoung, Baek, Kwang-Hyun

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A Review of Noise Reduction Techniques in Noise-shaping SAR ADCs von Seong, Kiho, Han, Jae-Soub, Kim, Sung-Eun, Shim, Yong, Baek, Kwang-Hyun

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A 3.2-GHz 178-fs rms Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier von Yoon, Dong-Hyun, Jung, Dong-Kyu, Seong, Kiho, Han, Jae-Soub, Chung, Keun-Yong, Kim, Ju-Eon, Kim, Tony Tae-Hyoung, Baek, Kwang-Hyun

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Direct digital frequency synthesizer capable of compensating frequency offset and minimizing spectral leakage von CHOI JI MIN, BAEK KWANG HYUN, HAN JAE SOUB, YOON DONG HYUN

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