Accurate Interpolation of Library Timing Parameters Through Recurrent Convolutional Neural Network von Hyun, Daijoon, Jung, Younggwang, Shin, Youngsoo

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Decap Insertion With Local Cell Relocation Minimizing IR-Drop Violations and Routing DRVs von Hyun, Daijoon, Jung, Younggwang, Shin, Youngsoo

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Airgap Insertion and Layer Reassignment Under Setup and Hold Timing Constraints von Hyun, Daijoon, Jung, Younggwang, Shin, Youngsoo

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Integrated Power Distribution Network Synthesis for Mixed Macro Blocks and Standard Cells von Hyun, Daijoon, Lee, Wonjae, Park, Jinhyeong, Shin, Youngsoo

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Selective Use of Stitch-Induced Via for V0 Mask Reduction: Standard Cell Design and Placement Optimization von HYUN, Daijoon, JUNG, Younggwang, SHIN, Youngsoo

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2D and Quasi-2D Halide Perovskite-Based Resistive Switching Memory Systems von Kim, Hyojung, Hyun, Daijoon, Hilal, Muhammad, Cai, Zhicheng, Moon, Cheon Woo

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Integrated Approach of Airgap Insertion for Circuit Timing Optimization von Hyun, Daijoon, Shin, Youngsoo

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Double Thresholding with Sine Entropy for Thermal Image Segmentation von Manda, Manikanta Prahlad, Hyun, Daijoon

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Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop Stacking von Hyun, Daijoon, Koh, Sunwha, Jung, Younggwang, Kim, Taeyoung, Shin, Youngsoo

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Cut Optimization for Redundant Via Insertion in Self-Aligned Double Patterning von Song, Youngsoo, Hyun, Daijoon, Lee, Jingon, Jung, Jinwook, Shin, Youngsoo

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Resistive random-access memories using quasi-2D halide perovskites for wafer-scale reliable switching behaviors von Kim, Hyojung, Choi, Min-ju, Suh, Jun Min, Shim, Young-Seok, Im, In Hyuk, Hyun, Daijoon, Yang, Seok Joo, Cai, Zhicheng, Hilal, Muhammad, Lee, Mi Gyoung, Moon, Cheon Woo, Kim, Soo Young, Jang, Ho Won

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Semiconductor device for testing large number of devices and composing method and test method thereof von Hyun, DaiJoon, Won, Hyosig, Jeong, Kwangok

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SEMICONDUCTOR DEVICE FOR TESTING LARGE NUMBER OF DEVICES AND COMPOSING METHOD AND TEST METHOD THEREOF von HYUN DAIJOON, JEONG KWANGOK, WON HYOSIG

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Method for forming semiconductor device for test and method for testing target transistors on front end of line-end-semiconductor device von WON, HYOSIG, HYUN, DAIJOON, JEONG, KWANGOK

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