A 10-Gb/s 16:1 multiplexer and 10-GHz clock synthesizer in 0.25-μm SiGe BiCMOS von Hong-Ih Cong, Logan, S.M., Loinaz, M.J., O'Brien, K.J., Perry, E.E., Polhemus, G.D., Scoggins, J.E., Snowdon, K.P., Ward, M.G.

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Effective on-current of MOSFETs for large-signal speed consideration von Ng, K.K., Rafferty, C.S., Hong-Ih Cong

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Multigigahertz CMOS dual-modulus prescalar IC von HONG-IH CONG, ANDREWS, J. M, BOULIN, D. M, SAN-CHIN FANG, HILLENIUS, S. J, MICHEJDA, J. A

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The Low-Noise 115-GHz Receiver on the Columbia-GISS 4-ft Radio Telescope von Hong-Ih Cong, Kerr, A.R., Mattauch, R.J.

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A high-performance directly insertable self-aligned ultra-rad-hard and enhanced isolation field-oxide technology for gigahertz silicon NMOS/CMOS VLSI von Manchanda, L., Hillenius, S.J., Lynch, W.T., Cong, H., Ng, K.K., Field, R.L.

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A 10-Gb/s 16:1 multiplexer and 10-GHz clock synthesizer in 0.25-[micro]m SiGe BiCMOS von Cong, Hong-Ih, Logan, S.M, Loinaz, M.J, O'Brien, K.J, Perry, E.E, Polhemus, G.D, Scoggins, J.E, Snowdon, K.P, Ward, M.G

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A 10-Gb/s 16:1 multiplexer and 10-GHz clock synthesizer in 0.25-/spl mu/m SiGe BiCMOS von Hong-Ih Cong, Logan, S.M., Loinaz, M.J., O'Brien, K.J., Perry, E.E., Polhemus, G.D., Scoggins, J.E., Snowdon, K.P., Ward, M.G.

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A 10-Gb/s 16:1 multiplexer and 10-GHz clock synthesizer in 0.25-mum SiGe BiCMOS von Cong, Hong-Ih, Logan, S M, Loinaz, M J, O' Brien, K J, Perry, E E, Polhemus, G D, Scoggins, J E, Snowdon, K P, Ward, M G

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A 10 Gb/s 16:1 multiplexer and 10 GHz clock synthesizer in 0.25 /spl mu/m SiGe BiCMOS von Hong-Ih Cong, Logan, S.M., Loinaz, M.J., O'Brien, K.J., Perry, E.E., Polhemus, G.D., Scoggins, J.E., Snowdon, K.P., Ward, M.G.

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Ultra-fast (0.5- mu m) CMOS circuits in fully depleted SOI films von Kamgar, A., Hillenius, S.J., Cong, H.-I.L., Field, R.L., Lindenberger, W.S., Celler, G.K., Trimble, L.E., Sheng, T.T.

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Non-volatile memory element for programmable logic applications von CONG, HONG-IH LOUIS, BUDE, JEFFREY DEVIN, MASTRAPASQUA, MARCO

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Non-volatile memory element for programmable logic applications and operational methods therefor von MASTRAPASQUA, MARCO, BUDE, JEFFREY DEVIN, CONG, HONG-IH LOUIS

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Impact of interconnect architecture on chip size and die yield von Liu, R., Pai, C.-S., Cong, H.-I., Lai, W., Martinez, E.

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Contributors, Mar. 1979 von Clauss, R.C., Hong-ih Cong, Gandhi, O.P., Howes, M.J., Jacobi, J.H., Johnson, K.M., Kerr, A.R., Kopeika, N.S., Lenox, R.H., Makover, Y., Mattauch, R.J., McBretney, J., Mehran, R., Meyerhoff, J.L., Moore, C.R., Pospieszalski, M.W., Schonbach, S., Smith, G.S., V.C.Y. So, Stegeman, G.I., G. A. Teh, Te-Kao Wu

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