In-situ electron holography of surface potential response to gate voltage application in a sub-30-nm gate-length metal-oxide-semiconductor field-effect transistor von Ikarashi, Nobuyuki, Takeda, Hiroshi, Yako, Koichi, Hane, Masami

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Statistical Compact Model Parameter Extraction by Direct Fitting to Variations von Takeuchi, K., Hane, M.

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Past and Future Technology for Mixed Signal LSI von HATASAKO, Kenichi, NITTA, Tetsuya, HANE, Masami, MAEGAWA, Shigeto

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Electron holography for analysis of deep submicron devices: Present status and challenges von Ikarashi, Nobuyuki, Toda, Akio, Uejima, Kazuya, Yako, Koichi, Yamamoto, Toyoji, Hane, Masami, Sato, Hiroshi

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Electron holography analysis of a shallow junction for planar-bulk metal-oxide-semiconductor field-effect transistors approaching the scaling limit von Ikarashi, Nobuyuki, Ikezawa, Takeshi, Uejima, Kazuya, Fukai, Toshinori, Miyamura, Makoto, Toda, Akio, Hane, Masami

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Millisecond Annealing Junctions for Near-Scaling-Limit Bulk CMOS Using Raised Source/Drain Extensions von Hane, Masami

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Effects of Selecting Channel Direction in Improving Performance of Sub-100 nm MOSFETs Fabricated on (110) Surface Si Substrate von Nakamura, Hidetatsu, Ezaki, Tatsuya, Iwamoto, Toshiyuki, Togo, Mitsuhiro, Ikezawa, Takeo, Ikarashi, Nobuyuki, Hane, Masami, Yamamoto, Toyoji

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Foreword Special Issue on Characterization of Nano CMOS Variability by Simulation and Measurements von Sangiorgi, Enrico, Asenov, Asen, Bennett, Herbert S., Dutton, Robert W., Esseni, David, Giles, Martin D., Hane, Masami, Nishi, Kenji, Ranaweera, Jeewika, Selberherr, Siegfried

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Characteristics and Modeling of Sub-10-nm Planar Bulk CMOS Devices Fabricated by Lateral Source/Drain Junction Control von Wakabayashi, H., Ezaki, T., Sakamoto, T., Kawaura, H., Ikarashi, N., Ikezawa, N., Narihiro, M., Ochiai, Y., Ikezawa, T., Takeuchi, K., Yamamoto, T., Hane, M., Mogami, T.

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Basic Performance of a Logic Intellectual Property Compatible Embedded Dynamic Random Access Memory with Cylinder Capacitors in Low-$k$/Cu Back End on the Line Layers von Kume, Ippei, Inoue, Naoya, Hijioka, Ken'ichiro, Kawahara, Jun, Takeda, Kouichi, Furutake, Naoya, Shirai, Hiroki, Kazama, Kenya, Kuwabara, Shin'ichi, Watarai, Msasatoshi, Sakoh, Takashi, Takahashi, Takafumi, Ogura, Takashi, Taiji, Toshiji, Kasama, Yoshiko, Sakamoto, Misato, Hane, Masami, Hayashi, Yoshihiro

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Basic Performance of a Logic Intellectual Property Compatible Embedded Dynamic Random Access Memory with Cylinder Capacitors in Low- k /Cu Back End on the Line Layers von Kume, Ippei, Inoue, Naoya, Hijioka, Ken'ichiro, Kawahara, Jun, Takeda, Kouichi, Furutake, Naoya, Shirai, Hiroki, Kazama, Kenya, Kuwabara, Shin'ichi, Watarai, Msasatoshi, Sakoh, Takashi, Takahashi, Takafumi, Ogura, Takashi, Taiji, Toshiji, Kasama, Yoshiko, Sakamoto, Misato, Hane, Masami, Hayashi, Yoshihiro

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Effects of drain bias on threshold voltage fluctuation and its impact on circuit characteristics von Miyamura, M., Nagumo, T., Takeuchi, K., Takeda, K., Hane, M.

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Electron Holography Characterization of Shallow Junction Fabricated By Diffusion-less Process for Sub-30 nm Gate-Length MOSFETs von Ikarashi, Nobuyuki, Toda, Akio, Uejima, Kazuya, Fukai, Toshinori, Hane, Masami, Ikezawa, Takeo

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Self-Consistent Quantum Mechanical Monte Carlo MOSFET Device Simulation von Ezaki, Tatsuya, Werner, Philipp, Hane, Masami

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Foreword Special Issue on Simulation and Modeling of Nanoelectronics Devices von Sangiorgi, Enrico, Asenov, Asen, Bennett, Herbert S., Dutton, Robert W., Esseni, David, Giles, Martin D., Hane, Masami, Jungemann, Christoph, Nishi, Kenji, Selberherr, Siegfried, Takagi, Shinichi

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Two-Step Inverse Modeling for Estimation of Channel Impurity Pile-up von Nagumo, Toshiharu, Takeuchi, Kiyoshi, Akiyama, Yutaka, Hane, Masami

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Model for Al etch-rate enhancement at low temperatures von UCHIDA, T, AOKI, H, HANE, M, HASEGAWA, S, IKAWA, E

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26 nm gate length CMOSFETs with aggressively reduced silicide position by using carbon cluster co-implanted raised source/drain extension structure von Yako, K., Yamamoto, T., Uejima, K., Hase, T., Hane, M.

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Source/drain engineering for high-performance deep sub-100nm Ge-pMOSFETs using Full-Band Monte Carlo simulation von Takeda, H., Ikezawa, T., Kawada, M., Hane, M.

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Characteristics and modeling of sub-10-nm planar bulk CMOS devices fabricated by lateral source/drain junction control : Advanced compact models and 45-nm modeling challenges von WAKABAYASHI, Hitoshi, EZAKI, Tatsuya, YAMAMOTO, Toyoji, HANE, Masami, MOGAMI, Tohru, SAKAMOTO, Toshitsugu, KAWAURA, Hisao, IKARASHI, Nobuyuki, IKEZAWA, Nobuyuki, NARIHIRO, Mitsuru, OCHIAI, Yukinori, IKEZAWA, Takeo, TAKEUCHI, Kiyoshi

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