Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis von Campbell, Keith, Lin, David, He, Leon, Yang, Liwei, Gurumani, Swathi T., Rupnow, Kyle, Mitra, Subhasish, Chen, Deming

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FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow von Yao Chen, Gurumani, Swathi T., Yun Liang, Guofeng Li, Donghui Guo, Rupnow, Kyle, Deming Chen

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High-Level Synthesis With Behavioral-Level Multicycle Path Analysis von Hongbin Zheng, Gurumani, Swathi T., Liwei Yang, Deming Chen, Rupnow, Kyle

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FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow von Ying Chen, Tan Nguyen, Yao Chen, Gurumani, Swathi T., Yun Liang, Rupnow, Kyle, Cong, Jason, Wen-Mei Hwu, Deming Chen

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High-level synthesis of multiple dependent CUDA kernels on FPGA von Gurumani, S. T., Cholakkal, H., Yun Liang, Rupnow, K., Deming Chen

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Hardware Coprocessor Synthesis from an ANSI C Specification von Ahuja, S., Gurumani, S.T., Spackman, C., Shukla, S.K.

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Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs von Chen, Deming, Cong, Jason, Gurumani, Swathi, Hwu, Wen‐mei, Rupnow, Kyle, Zhang, Zhiru

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New Solutions for Cross-Layer System-Level and High-Level Synthesis von Zuo, Wei, Gurumani, Swathi, Rupnow, Kyle, Chen, Deming

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