Field mapping of focused ion beam prepared semiconductor devices by off-axis and dark field electron holography von Cooper, David, Rivallin, Pierrette, Guegan, Georges, Plantier, Christophe, Robin, Eric, Guyot, Florence, Constant, Isabelle

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SOI 1T-DRAM cells with variable channel length and thickness: Experimental comparison of programming mechanisms von Hubert, Alexandre, Bawedin, Maryline, Guegan, Georges, Ernst, Thomas, Faynot, Olivier, Cristoloveanu, Sorin

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Low temperature dielectric relaxation and charged defects in ferroelectric thin films von Artemenko, A., Payan, S., Rousseau, A., Levasseur, D., Arveux, E., Guegan, G., Maglione, M.

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Experimental comparison of programming mechanisms in 1T-DRAM cells with variable channel length von Hubert, Alexandre, Bawedin, Maryline, Guegan, Georges, Cristoloveanu, Sorin, Ernst, Thomas, Faynot, Olivier

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Three level charge pumping on a single interface trap von Militaru, L., Masson, P., Guegan, G.

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65nm Low Power (LP) SOI Technology on High Resistivity (HR) Substrate for WLAN and Mmwave SOCs von Raynaud, Christine, Haendler, Sebastien, Guegan, Georges, Gianesello, Frederic, Martineau, Baudouin, Touret, Patricia, Planes, Nicolas

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New floating-body effect in partially depleted SOI pMOSFET due to direct-tunneling current in the partial n+ poly gate von Guegan, Georges, Gwoziecki, R., Touret, P., Raynaud, C., Pretet, J., Gonnard, O., Gouget, G., Deleonibus, S.

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Analysis of PD SOI pMOSFET Device Performance Enhancement due to Direct-Tunneling Current in the Partial n+ Poly Gate von Guegan, Georges, Pretet, Jeremy, Gwoziecki, Romain, Gonnard, Olivier, Gouget, Gilles, Touret, Patricia, Raynaud, Christine, Deleonibus, Simon

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Capacitorless DRAM memory cell comprising a partially-depleted MOSFET device comprising a gate insulator in two parts von GUEGAN GEORGES

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DISPOSITIF DE TYPE MOSFET PARTIELLEMENT DESERTE COMPORTANT UN ISOLANT DE GRILLE EN DEUX PARTIES ET UTILISATION COMME CELLULE DE MEMOIRE von GUEGAN GEORGES

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Capacitorless DRAM memory cell comprising a partially-depleted MOSFET device comprising a gate insulator in two parts von GUEGAN GEORGES

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Method of producing a semi-conductor with a highly doped zone situated between lightly doped zones, for the manufacture of transistors von GUEGAN, GEORGES

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PROCEDE DE REALISATION D'UN SEMI-CONDUCTEUR AVEC UNE ZONE FORTEMENT DOPEE SITUEE ENTRE DES ZONES FAIBLEMENT DOPEES, POUR LA FABRICATION DE TRANSISTORS von GUEGAN GEORGES

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Process for manufacturing transistors von GUEGAN, GEORGES

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Operation of short-channel depletion-mode MOS devices at liquid-nitrogen temperature von Gautier, J., Guegan, G., Guerin, M., Lerme, M.

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DISPOSITIF DE TYPE MOSFET PARTIELLEMENT DESERTE COMPORTANT UN ISOLANT DE GRILLE EN DEUX PARTIES ET UTILISATION COMME CELLULE DE MEMOIRE von GUEGAN GEORGES

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Capacitorless dynamic RAM type memory cell for storing information, has MOSFET type device with substrate having grid insulator comprising two parts of equal thickness, where one p... von GUEGAN GEORGES

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DRAM memory cell with no capacitance made up of a partially deserted MOSFET-type device comprising a gate insulator in two parts von GUEGAN, GEORGES

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65nm Low Power (LP) SOI technology on HR substrate for WLAN and Mmwave SOCs von Raynaud, Christine, Haendler, Sebastien, Guegan, Georges, Gianesello, Frederic, Martineau, Baudouin, Touret, Patricia, Planes, Nicolas

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METHOD OF MANUFACTURING A MIS TRANSISTOR ON A SEMICONDUCTOR SUBSTRATE von DELEONIBUS, SIMON, COUDERT, FABIEN, CAILLAT, CHRISTIAN, GUEGAN, GEORGES

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