Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability von Wei Hwang, Gristede, G., Sanda, P., Wang, S.Y., Heidel, D.F.

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A scannable pulse-to-static conversion register array for self-timed circuits von Wei Hwang, Joshi, R.V., Gristede, G.D.

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Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design von Chen, W., Hwang, W., Kudva, P., Gristede, G., Kosonocky, S., Joshi, R.

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Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies von Chin, Phillip, Zukowski, Charles A., Gristede, George D., Kosonocky, Stephen V.

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Measuring error propagation in waveform relaxation algorithms von Zukowski, C., Gristede, G., Ruehli, A.

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Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design von Chen, W., Hwang, W., Kudva, R., Gristede, G.D., Kosonocky, S., Joshi, R.V.

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Design and implementation of high performance dynamic 64-bit parallel adder with enhanced testability von Hwang, W., Gristede, G.D., Sanda, P.N., Wang, S.Y., Heidel, D.F.

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A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR) von Vratonjić, Milena, Ziegler, Matthew, Gristede, George D., Zyuban, Victor, Mitchell, Thomas, Cho, Ee, Visweswariah, Chandu, Oklobdzija, Vojin G.

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