An experimental 1-Mbit CMOS SRAM with configurable organization and operation von Williams, T., Beilstein, K., El-Kareh, B., Flaker, R., Gravenites, G., Lipa, R., Lee, H.-S., Maslack, J., Pessetto, J., Pokorny, W.F., Roberge, M., Zeller, H.

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