Treffer 1 - 5 von 5 für Suche 'Gowreesrinivas, K. V.', Suchdauer: 0,35s Treffer weiter einschränken
  1. 1
    FPGA Implementation of a Resource Efficient Vedic Multiplier using SPST Adders

    FPGA Implementation of a Resource Efficient Vedic Multiplier using SPST Adders von Gowreesrinivas, K. V., Srinivas, Sabbavarapu, Samundiswary, Punniakodi


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  2. 2
    FPGA Implementation of Single-Precision Floating Point Multiplication with Karatsuba Algorithm Using Vedic Mathematics

    FPGA Implementation of Single-Precision Floating Point Multiplication with Karatsuba Algorithm Using Vedic Mathematics von Gowreesrinivas, K. V., Samundiswary, P.


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  3. 3
    Performance Efficient Floating-Point Multiplication Using Unified Adder–Subtractor-Based Karatsuba Algorithm

    Performance Efficient Floating-Point Multiplication Using Unified Adder–Subtractor-Based Karatsuba Algorithm von Gowreesrinivas, K. V., Samundiswary, P.


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  4. 4
    A Safe and Cost-Effective Algorithm for Automation of LPG Cylinder Booking Using ESP8266

    A Safe and Cost-Effective Algorithm for Automation of LPG Cylinder Booking Using ESP8266 von Nalla, Srinivasa Naidu, Gowreesrinivas, K. V.


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  5. 5
    Design and Analysis of Single Precision Floating Point Multiplication with Vedic Mathematics Using Different Techniques

    Design and Analysis of Single Precision Floating Point Multiplication with Vedic Mathematics Using Different Techniques von Gowreesrinivas, K. V., Samundiswary, P.


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