Instruction buffering to reduce power in processors for signal processing von Bajwa, R.S., Hiraki, M., Kojima, H., Gorny, D.J., Nitta, K., Shridhar, A., Seki, K., Sasaki, K.

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Power analysis of a programmable DSP for architecture/program optimization von Kojima, H., Gorny, D.J., Nitta, K., Sasaki, K.

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Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer von Hiraki, M., Bajwa, R.S., Kojima, H., Gorny, D.J., Nitta, K., Shri, A.

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Reproductive biology of caridean decapods from the Weddell Sea von GORNY, M, ARNTZ, W. E, CLARKE, A, GORE, D. J

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