Microscopy study of the conductive filament in HfO2 resistive switching memory devices von Privitera, S., Bersuker, G., Butcher, B., Kalantarian, A., Lombardo, S., Bongiorno, C., Geer, R., Gilmer, D.C., Kirsch, P.D.

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Fermi-level pinning at the polysilicon/metal oxide interface-Part I von Hobbs, C.C., Fonseca, L.R.C., Knizhnik, A., Dhandapani, V., Samavedam, S.B., Taylor, W.J., Grant, J.M., Dip, L.G., Triyoso, D.H., Hegde, R.I., Gilmer, D.C., Garcia, R., Roan, D., Lovejoy, M.L., Rai, R.S., Hebert, E.A., Hsing-Huang Tseng, Anderson, S.G.H., White, B.E., Tobin, P.J.

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Mechanisms Limiting EOT Scaling and Gate Leakage Currents of High- k/Metal Gate Stacks Directly on SiGe von Huang, J., Kirsch, P.D., Jungwoo Oh, Se Hoon Lee, Majhi, P., Harris, H.R., Gilmer, D.C., Bersuker, G., Dawei Heh, Chang Seo Park, Park, C., Hsing-Huang Tseng, Jammy, R.

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Erase and Retention Improvements in Charge Trap Flash Through Engineered Charge Storage Layer von Goel, N., Gilmer, D.C., Park, H., Diaz, V., Sun, Y., Price, J., Park, C., Pianetta, P., Kirsch, P.D., Jammy, R.

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Fermi-level pinning at the polysilicon/metal-oxide interface-Part II von Hobbs, C.C., Fonseca, L.R.C., Knizhnik, A., Dhandapani, V., Samavedam, S.B., Taylor, W.J., Grant, J.M., Dip, L.G., Triyoso, D.H., Hegde, R.I., Gilmer, D.C., Garcia, R., Roan, D., Lovejoy, M.L., Rai, R.S., Hebert, E.A., Hsing-Huang Tseng, Anderson, S.G.H., White, B.E., Tobin, P.J.

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Conductive filament structure in HfO2 resistive switching memory devices von Privitera, S., Bersuker, G., Lombardo, S., Bongiorno, C., Gilmer, D.C.

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High Dielectric Constant Materials: VLSI MOSFET Applications von Huff, H.R, Gilmer, D.C

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Strained SiGe Channels for Band-Edge PMOS Threshold Voltages With Metal Gates and High- k Dielectrics von Gilmer, D.C., Schaeffer, J.K., Taylor, W.J., Capasso, C., Junker, K., Hildreth, J., Tekleab, D., Winstead, B., Samavedam, S.B.

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Application of group electronegativity concepts to the effective work functions of metal gate electrodes on high- κ gate oxides von Schaeffer, J.K., Gilmer, D.C., Capasso, C., Kalpat, S., Taylor, B., Raymond, M.V., Triyoso, D., Hegde, R., Samavedam, S.B., White, B.E.

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Gate first high-k/metal gate stacks with zero SiOx interface achieving EOT=0.59nm for 16nm application von Huang, J., Heh, D., Sivasubramani, P., Kirsch, P.D., Bersuker, G., Gilmer, D.C., Quevedo-Lopez, M.A., Hussain, M.M., Majhi, P., Lysaght, P., Park, H., Goel, N., Young, C., Park, C.S., Park, C., Cruz, M., Diaz, V., Hung, P.Y., Price, J., Tseng, H.-H., Jammy, R.

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Mechanisms Limiting EOT Scaling and Gate Leakage Currents of High- [Formula Omitted]/Metal Gate Stacks Directly on SiGe von Huang, J, Kirsch, P.D, Oh, Jungwoo, Lee, Se Hoon, Majhi, P, Harris, H.R, Gilmer, D.C, Bersuker, G, Heh, Dawei, Park, Chang Seo, Park, C, Tseng, Hsing-Huang, Jammy, R

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Compatibility of silicon gates with hafnium-based gate dielectrics von Gilmer, D.C., Hegde, R., Cotton, R., Smith, J., Dip, L., Garcia, R., Dhandapani, V., Triyoso, D., Roan, D., Franke, A., Rai, R., Prabhu, L., Hobbs, C., Grant, J.M., La, L., Samavedam, S., Taylor, B., Tseng, H., Tobin, P.

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Mechanisms limiting EOT scaling and gate leakage currents of high-k/metal gate stacks directly on SiGe and a method to enable sub-1nm EOT von Huang, J., Kirsch, P.D., Oh, J., Lee, S.H., Price, J., Majhi, P., Harris, H.R., Gilmer, D.C., Kelly, D.Q., Sivasubramani, P., Bersuker, G., Heh, D., Young, C., Park, C.S., Tan, Y.N., Goel, N., Park, C., Hung, P.Y., Lysaght, P., Choi, K.J., Cho, B.J., Tseng, H-H., Lee, B.H., Jammy, R.

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LASER Anneal to Enable Ultimate CMOS Scaling with PMOS Band Edge Metal Gate/High-K Stacks von Gilmer, D.C., Schaeffer, J.K., Taylor, W.J., Spencer, G., Triyoso, D.H., Raymond, M., Roan, D., Smith, J., Capasso, C., Hegde, R.I., Samavedam, S.B.

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9 - Metal oxide resistive random access memory (RRAM) technology von Bersuker, G., Gilmer, D.C.

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Modeling the effects of different forming conditions on RRAM conductive filament stability von Butcher, B., Bersuker, G., Vandelli, L., Padovani, A., Larcher, L., Kalantarian, A., Geer, R., Gilmer, D. C.

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High-k Crystalline Gate Dielectrics: A Research Perspective von Walker, F.J., McKee, R.A.

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MOSFET transistors fabricated with high permitivity TiO/sub 2/ dielectrics von Campbell, S.A., Gilmer, D.C., Xiao-Chuan Wang, Ming-Ta Hsieh, Hyeon-Seag Kim, Gladfelter, W.L., Jinhua Yan

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Optimal Scaling Methodologies and Transistor Performance von Skotnicki, T., Boeuf, F.

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Materials Issues for High-k Gate Dielectric Selection and Integration von Wallace, R.M., Wilk, G.D.

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