Transient-induced latch-up test setup for wafer-level and package-level von Bonfert, D., Gieser, H., Wolf, H., Frank, M., Konrad, A., Schulz, J.

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Transient latch-up: experimental analysis and device simulation von Bargstädt-Franke, S., Stadler, W., Esmark, K., Streibl, M., Domanski, K., Gieser, H., Wolf, H., Bala, W.

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Study of CDM specific effects for a smart power input protection structure von Etherton, M., Qu, N., Willemen, J., Wilkening, W., Mettler, S., Dissegna, M., Stella, R., Zullino, L., Andreini, A., Gieser, H., Wolf, H., Fichtner, W.

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Characterization and modeling of transient device behavior under CDM ESD stress von Willemen, J., Andreini, A., De Heyn, V., Esmark, K., Etherton, M., Gieser, H., Groeseneken, G., Mettler, S., Morena, E., Qu, N., Soppa, W., Stadler, W., Stella, R., Wilkening, W., Wolf, H., Zullino, L.

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Transient induced latch-up triggered by very fast pulses von Bonfert, D., Gieser, H.

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Test circuits for fast and reliable assessment of CDM robustness of I/O stages von Stadler, W., Esmark, K., Reynders, K., Zubeidat, M., Graf, M., Wilkening, W., Willemen, J., Qu, N., Mettler, S., Etherton, M., Nuernbergk, D., Wolf, H., Gieser, H., Soppa, W., De Heyn, V., Natarajan, M., Groeseneken, G., Morena, E., Stella, R., Andreini, A., Litzenberger, M., Pogany, D., Gornik, E., Foss, C., Konrad, A., Frank, M.

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Investigation of ESD protection elements under high current stress in CDM-like time domain using backside laser interferometry von Bychikhin, S., Dubec, V., Litzenberger, M., Pogany, D., Gornik, E., Groos, G., Esmark, K., Stecher, M., Stadler, W., Gieser, H., Wolf, H.

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Pulsed thermal characterization of a reverse biased pn-junction for ESD HBM simulation von Wolf, H., Gieser, H., Wilkening, W.

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Risetime effects of HBM and square pulses on the failure thresholds of GGNMOS-transistors von Musshoff, C., Wolf, H., Gieser, H., Egger, P., Guggenmos, X.

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ESD circuit simulation for the prevention of ESD failures: Application to products in a 0.18 μm CMOS technology von WOLF, Heinrich, GIESER, Horst, STADLER, Wolfgang, ESMARK, Kai

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Does the ESD-failure current obtained by transmission-line pulsing always correlate to human body model tests? von Stadler, W, Guggenmos, X, Egger, P, Gieser, H, Musshoff, C

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Investigation into socketed CDM (SDM) tester parasitics von Chaine, M, Verhaege, K, Avery, L, Kelly, M, Gieser, H, Bock, K, Henry, L.G, Meuse, T, Brodbeck, T, Barth, J

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Capacitively coupled transmission line pulsing cc-TLP––a traceable and reproducible stress method in the CDM-domain von Wolf, Heinrich, Gieser, Horst, Stadler, Wolfgang, Wilkening, Wolfgang

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Electrical stress on film resistive structures on flexible substrates von Bonfert, D, Klink, G, Gieser, H, Bock, K, Svasta, P, Ionescu, C

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A Dedicated TLP Set-Up to Investigate the ESD Robustness of RF Elements and Circuits von Wolf, Heinrich, Gieser, Horst, Soldner, Wolfgang, Goßner, Harald

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InterChip via technology for vertical system integration von Ramm, P., Bonfert, D., Gieser, H., Haufe, J., Iberl, F., Klumpp, A., Kux, A., Wieland, R.

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Rapid prototyping of electronic modules combining Aerosol printing and Ink Jet printing von Gieser, H A, Bonfert, D, Hengelmann, H, Wolf, H, Bock, K, Zollmer, V, Werner, C, Domann, G, Bahr, J, Ndip, I, Curran, B, Oehler, F, Milosiu, H

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Analyzing the switching behavior of ESD-protection transistors by very fast transmission line pulsing von Wolf, Heinrich, Gieser, Horst, Wilkening, Wolfgang

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On-chip electrostatic discharge ESD von Gieser, Horst A.

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Electrostatic Discharge - ESD von Gieser, H., Worley, E.

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