Guest Editors' Introduction: Special Section on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems von Metra, Cecilia, Galivanche, Rajesh

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Path coverage based functional test generation for processor marginality validation von Natarajan, S, Krishnamachary, A, Chiprout, E, Galivanche, R

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New Approaches for Power Binning of High Performance Microprocessors von Omana, Martin, Padovani, Marco, Veliu, Kreshnik, Metra, Cecilia, Alt, Juergen, Galivanche, Rajesh

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Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST von Omana, Martin, Rossi, Daniele, Fuzzi, Filippo, Metra, Cecilia, Tirumurti, Chandrasekharan Chandra, Galivanche, Rajesh

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Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST von Omaña, Martin, Rossi, Daniele, Beniamino, Edda, Metra, Cecilia, Tirumurti, Chandrasekharan, Galivanche, Rajesh

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Global Signal Vulnerability (GSV) Analysis for Selective State Element Hardening in Modern Microprocessors von Maniatakos, M., Tirumurti, C., Galivanche, R., Makris, Y.

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Bridging pre-silicon verification and post-silicon validation von Nahir, Amir, Ziv, Avi, Abramovici, Miron, Camilleri, Albert, Galivanche, Rajesh, Bentley, Bob, Foster, Harry, Hu, Alan, Bertacco, Valeria, Kapoor, Shakti

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Is the concern for soft-error overblown? von Galivanche, R.

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A low-cost concurrent error detection technique for processor control logic von Vemu, R., Jas, A., Abraham, J.A., Patil, S., Galivanche, R.

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Testing in the year 2020 von Galivanche, Rajesh, Kapur, Rohit, Rubio, Antonio

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Trends in manufacturing test methods and their implications von Kundu, S., Mak, T.M., Galivanche, R.

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Testing in the Year 2020 von Galivanche, R., Kapur, R., Rubio, A.

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Is the concern for soft-error overblown? von Kundu, Sandip

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Test Challenges in Nanometer Technologies von Kundu, Sandip, Zachariah, Sujit T, Sengupta, Sanjay, Galivanche, Rajesh

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Circuit and platform design challenges in technologies beyond 90nm von Grundmann, B., Galivanche, R., Kundu, S.

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Circuit and Platform Design Challenges in Technologies beyond 90nm von Grundmann, Bill, Galivanche, Rajesh, Kundu, Sandip

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The Challenges of Nanotechnology and Gigacomplexity von Singer, G., Galivanche, R., Patil, S., Tripp, M.

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Device, system, and method for optimized concurrent error detection von GALIVANCHE RAJESH, JAS ABHIJIT, PATIL SRINIVAS, VEMU RAMTILAK

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Device, system, and method for optimized concurrent error detection von Jas, Abhijit, Patil, Srinivas, Galivanche, Rajesh, Vemu, Ramtilak

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Dft technique for avoiding contention/conflict in logic built-in self-test von GALIVANCHE RAJESH, KUNDU SANDIP, SENGUPTA SANJAY

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