Graph-Based Compact Model (GCM) for Efficient Transistor Parameter Extraction: A Machine Learning Approach on 12 nm FinFETs von Yang, Ziyao, Gaidhane, Amol D., Anderson, Kassandra, Workman, Glenn, Cao, Yu

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Gate-Induced Drain Leakage in Negative Capacitance FinFETs von Gaidhane, Amol D., Pahwa, Girish, Verma, Amit, Chauhan, Yogesh Singh

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Universal Compact Model of Flicker Noise in Ferroelectric Logic and Memory Transistors von Kumar, Abhishek, Ehteshamuddin, M., Gaidhane, Amol D., Bulusu, Anand, Mehrotra, Shruti, Dasgupta, Avirup

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Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology von Amrouch, Hussam, Pahwa, Girish, Gaidhane, Amol D., Dabhi, Chetan K., Klemme, Florian, Prakash, Om, Chauhan, Yogesh Singh

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A Computationally Efficient Compact Model for Ferroelectric Switching With Asymmetric Nonperiodic Input Signals von Gaidhane, Amol D., Dangi, Raghvendra, Sahay, Shubham, Verma, Amit, Chauhan, Yogesh Singh

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Unveiling the Impact of IR-Drop on Performance Gain in NCFET-Based Processors von Amrouch, Hussam, Salamin, Sami, Pahwa, Girish, Gaidhane, Amol D., Henkel, Jorg, Chauhan, Yogesh S.

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Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance von Amrouch, Hussam, Pahwa, Girish, Gaidhane, Amol D., Henkel, Jorg, Chauhan, Yogesh Singh

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Design Exploration of 14 nm FinFET for Energy-Efficient Cryogenic Computing von Gaidhane, Amol D., Saligram, Rakshith, Chakraborty, Wriddhi, Datta, Suman, Raychowdhury, Arijit, Cao, Yu

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Compact Modeling of Surface Potential, Drain Current and Terminal Charges in Negative Capacitance Nanosheet FET including Quasi-Ballistic Transport von Gaidhane, Amol D., Pahwa, Girish, Dasgupta, Avirup, Verma, Amit, Chauhan, Yogesh Singh

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Physics-constrained graph modeling for building thermal dynamics von Yang, Ziyao, Gaidhane, Amol D., Drgoňa, Ján, Chandan, Vikas, Halappanavar, Mahantesh M., Liu, Frank, Cao, Yu

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Compact Modeling of Drain Current, Charges, and Capacitances in Long-Channel Gate-All-Around Negative Capacitance MFIS Transistor von Gaidhane, Amol D., Pahwa, Girish, Verma, Amit, Chauhan, Yogesh Singh

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Graph-based Compact Modeling (GCM) of CMOS transistors for efficient parameter extraction: A machine learning approach von Gaidhane, Amol D., Yang, Ziyao, Cao, Yu

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Graph-based Compact Modeling (GCM) of CMOS transistors for efficient parameter extraction: A machine learning approach von Gaidhane, Amol D., Yang, Ziyao, Cao, Yu

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Ferroelectric FET-Based Time-Mode Multiply-Accumulate Accelerator: Design and Analysis von Rafiq, Musaib, Kaur, Tanveer, Gaidhane, Amol, Chauhan, Yogesh Singh, Sahay, Shubham

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Ferroelectric FET-Based Implementation of FitzHugh-Nagumo Neuron Model von Rajasekharan, Dinesh, Gaidhane, Amol, Trivedi, Amit Ranjan, Chauhan, Yogesh Singh

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Temperature- and variability-aware compact modeling of ferroelectric FDSOI FET for memory and emerging applications von Chatterjee, Swetaki, Kumar, Shubham, Gaidhane, Amol, Dabhi, Chetan Kumar, Chauhan, Yogesh Singh, Amrouch, Hussam

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Ferroelectric FDSOI FET modeling for memory and logic applications von Chatterjee, Swetaki, Kumar, Shubham, Gaidhane, Amol, Dabhi, Chetan Kumar, Chauhan, Yogesh Singh, Amrouch, Hussam

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Assessing Negative-Capacitance Drain-Extended Technology for High-Voltage Switching and Analog Applications von Pahwa, Girish, Gaidhane, Amol Domaji, Agarwal, Amit, Chauhan, Yogesh Singh

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A Computationally Efficient Compact Model for Ferroelectric Switching with Asymmetric Non-Periodic Input Signals von Gaidhane, Amol D., Dangi, Raghvendra, Sahay, Shubham, Verma, Amit, Chauhan, Yogesh Singh

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Study of multi-domain switching dynamics in negative capacitance FET using SPICE model von Gaidhane, Amol D., Verma, Amit, Chauhan, Yogesh Singh

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