Treffer 1 - 6 von 6 für Suche 'GURRAM KRISHNA CHAITHANYA', Suchdauer: 0,90s Treffer weiter einschränken
  1. 1
    Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory scheme

    Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory scheme von TRAN JONATHAN (SON) HUNG, GURRAM KRISHNA CHAITHANYA, ZBICIAK JOSEPH RAYMOND MICHAEL, CHACHAD ABHIJEET ASHOK

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  2. 2
    Hazard prevention for data conflicts between level one data cache line allocates and snoop writes

    Hazard prevention for data conflicts between level one data cache line allocates and snoop writes von TRAN JONATHAN (SON) HUNG, GURRAM KRISHNA CHAITHANYA, CHACHAD ABHIJEET ASHOK, DAMODARAN RAGURAM

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  3. 3
    Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routines

    Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routines von TRAN JONATHAN (SON) HUNG, GURRAM KRISHNA CHAITHANYA, CHACHAD ABHIJEET ASHOK, DAMODARAN RAGURAM

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  4. 4
    CONFIGURABLE SOURCE BASED/REQUESTOR BASED ERROR DETECTION AND CORRECTION FOR SOFT ERRORS IN MULTI-LEVEL CACHE MEMORY TO MINIMIZE CPU INTERRUPT SERVICE ROUTINES

    CONFIGURABLE SOURCE BASED/REQUESTOR BASED ERROR DETECTION AND CORRECTION FOR SOFT ERRORS IN MULTI-LEVEL CACHE MEMORY TO MINIMIZE CPU INTERRUPT SERVICE ROUTINES von TRAN JONATHAN (SON) HUNG, GURRAM KRISHNA CHAITHANYA, CHACHAD ABHIJEET ASHOK, DAMODARAN RAGURAM

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  5. 5
    Hazard Prevention for Data Conflicts Between Level One Data Cache Line Allocates and Snoop Writes

    Hazard Prevention for Data Conflicts Between Level One Data Cache Line Allocates and Snoop Writes von TRAN JONATHAN (SON) HUNG, GURRAM KRISHNA CHAITHANYA, CHACHAD ABHIJEET ASHOK, DAMODARAN RAGURAM

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  6. 6
    Robust Hamming Code Implementation for Soft Error Detection, Correction, and Reporting in a Multi-Level Cache System Using Dual Banking Memory Scheme

    Robust Hamming Code Implementation for Soft Error Detection, Correction, and Reporting in a Multi-Level Cache System Using Dual Banking Memory Scheme von TRAN JONATHAN (SON) HUNG, GURRAM KRISHNA CHAITHANYA, ZBICIAK JOSEPH RAYMOND MICHAEL, CHACHAD ABHIJEET ASHOK

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