Placement of thermal vias in 3-D ICs using various thermal objectives von Goplen, B., Sapatnekar, S.S.

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Temperature-Aware Placement for SOCs von Jeng-Liang Tsai, Chen, C.C.-P., Guoqiang Chen, Goplen, B., Haifeng Qian, Yong Zhan, Sung-Mo Kang, Wong, M.D.F., Sapatnekar, S.S.

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Placement of 3D ICs with thermal and interlayer via considerations von Goplen, Brent, Spatnekar, Sachin

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Temperature-aware placement for SOCs: On-chip thermal engineering von TSAI, Jeng-Liang, CHEN, Charlie Chung-Ping, GUOQIANG CHEN, GOPLEN, Brent, HAIFENG QIAN, YONG ZHAN, KANG, Sung-Mo, WONG, Martin D. F, SAPATNEKAR, Sachin S

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Net weighting to reduce repeater counts during placement von Goplen, Brent, Saxena, Prashant, Sapatnekar, Sachin

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Placement and routing in 3D integrated circuits von Ababei, C., Feng, Y., Goplen, B., Hushrav Mogal, Zhang, T., Bazargan, K., Sachin Sapatnekar

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Parameter variation improvement von GOPLEN BRENT A, BASHABOINA PAVAN Y, LANDIS HOWARD S

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Electrothermal analysis and optimization techniques for nanoscale integrated circuits von Zhan, Yong, Goplen, Brent, Sapatnekar, Sachin S.

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Integrated circuit and design structure having reduced through silicon via-induced stress von Kinsman Brian L, Sprogis Edmund J, Rassel Robert M, Vanslette Daniel S, Goplen Brent A, Bonn Jeffrey P

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PARAMETER VARIATION IMPROVEMENT von GOPLEN BRENT A, BASHABOINA PAVAN Y, LANDIS HOWARD S

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INTEGRATED CIRCUIT AND DESIGN STRUCTURE HAVING REDUCED THROUGH SILICON VIA-INDUCED STRESS von BONN JEFFREY P, GOPLEN BRENT A, VANSLETTE DANIEL S, KINSMAN BRIAN L, RASSEL ROBERT M, SPROGIS EDMUND J

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