A survey of algorithmic methods in IC reverse engineering von Azriel, Leonid, Speith, Julian, Albartus, Nils, Ginosar, Ran, Mendelson, Avi, Paar, Christof

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QNoC: QoS architecture and design process for network on chip von Bolotin, Evgeny, Cidon, Israel, Ginosar, Ran, Kolodny, Avinoam

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GIRAF: General Purpose In-Storage Resistive Associative Framework von Yavits, Leonid, Kaplan, Roman, Ginosar, Ran

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RASSA: Resistive Prealignment Accelerator for Approximate DNA Long Read Mapping von Kaplan, Roman, Yavits, Leonid, Ginosar, Ran

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A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment von Kaplan, Roman, Yavits, Leonid, Ginosar, Ran, Weiser, Uri

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PRINS: Processing-in-Storage Acceleration of Machine Learning von Kaplan, Roman, Yavits, Leonid, Ginosar, Ran

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Computer Architecture with Associative Processor Replacing Last-Level Cache and SIMD Accelerator von Yavits, Leonid, Morad, Amir, Ginosar, Ran

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A Model for Supply Voltage and Temperature Variation Effects on Synchronizer Performance von Beer, Salomon, Ginosar, Ran

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Eleven Ways to Boost Your Synchronizer von Beer, Salomon, Ginosar, Ran

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Accelerator for Sparse Machine Learning von Yavits, Leonid, Ginosar, Ran

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Timing–driven variation–aware synthesis of hybrid mesh/tree clock distribution networks von Abdelhadi, Ameer, Ginosar, Ran, Kolodny, Avinoam, Friedman, Eby G.

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Enabling Full Associativity with Memristive Address Decoder von Yavits, Leonid, Kaplan, Roman, Ginosar, Ran

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Network Delays and Link Capacities in Application-Specific Wormhole NoCs von Guz, Zvika, Walter, Isask'har, Bolotin, Evgeny, Cidon, Israel, Ginosar, Ran, Kolodny, Avinoam

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GP-SIMD Processing-in-Memory von Morad, Amir, Yavits, Leonid, Ginosar, Ran

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Scalable network-on-chip architecture for configurable neural networks von Vainbrand, Dmitri, Ginosar, Ran

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Resistive Associative Processor von Yavits, Leonid, Kvatinsky, Shahar, Morad, Amir, Ginosar, Ran

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Using Scan Side Channel to Detect IP Theft von Azriel, Leonid, Ginosar, Ran, Gueron, Shay, Mendelson, Avi

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SafeRazor: Metastability-Robust Adaptive Clocking in Resilient Circuits von Cannizzaro, Marco, Beer, Salomon, Cortadella, Jordi, Ginosar, Ran, Lavagno, Luciano

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Resistive GP-SIMD Processing-In-Memory von Morad, Amir, Yavits, Leonid, Kvatinsky, Shahar, Ginosar, Ran

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High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link von Dobkin, R., Perelman, Y., Liran, T., Ginosar, R., Kolodny, A.

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