Integration of multiple gate dielectrics by surface protection von LIM SANGWOO, YEAP GEOFFREY (CHOH-FEI), KANG LAEGU

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Integration of multiple gate dielectrics by surface protection von Lim, Sangwoo, Kang, Laegu, Yeap, Geoffrey (Choh-Fei)

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MOS device with self-compensating VaT-implants von MILIC-STRKALJ, OGNJEN, YEAP, GEOFFREY CHOH-FEI

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Ultra-shallow p-type junction having reduced sheet resistance and method for producing shallow junctions von SULTAN, AKIF, YEAP, GEOFFREY CHOH-FEI

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Semiconductor with laterally non-uniform channel doping profile and manufacturing method therefor von Yeap, Geoffrey Choh-Fei, Milic, Ognjen, Ng, Che-Hoo

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Ultra-thin oxide for semiconductors von LIN, MING-REN, YEAP, GEOFFREY CHOH-FEI, KRIVOKAPIC, ZORAN

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Semiconductor device having enhanced gate capacitance by using both high and low dielectric materials von KRISHNAN, SRINATH, BUYNOSKI, MATTHEW, YEAP, GEOFFREY CHOH-FEI, KRIVOKAPIC, ZORAN

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Formation of low resistance, ultra shallow LDD junctions employing a sub-surface, non-amorphous implant von SULTAN, AKIF, YEAP, GEOFFREY CHOH-FEI, PRAMANICK, SHEKHAR

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Method for increasing gate capacitance by using both high and low dielectric gate material von KRISHNAN, SRINATH, BUYNOSKI, MATTHEW, YEAP, GEOFFREY CHOH-FEI, KRIVOKAPIC, ZORAN

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Semiconductor with laterally non-uniform channel doping profile and manufacturing method therefor von MILIC OGNJEN, NG CHE-HOO, YEAP GEOFFREY CHOH-FEI

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Semiconductor with laterally non-uniform channel doping profile von MILIC OGNJEN, NG CHE-HOO, YEAP GEOFFREY CHOH-FEI

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CMOS optimization method utilizing sacrificial sidewall spacer von XIANG, QI, LIN, MING-REN, YEAP, GEOFFREY CHOH-FEI

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