A Review of Low Temperature Process Modules Leading Up to the First (≤500 °C) Planar FDSOI CMOS Devices for 3-D Sequential Integration von Fenouillet-Beranger, C., Brunet, L., Batude, P., Brevard, L., Garros, X., Casse, M., Lacord, J., Sklenard, B., Acosta-Alba, P., Kerdiles, S., Tavernier, A., Vizioz, C., Besson, P., Gassilloud, R., Pedini, J.-M., Kanyandekwe, J., Mazen, F., Magalhaes-Lucas, A., Cavalcante, C., Bosch, D., Ribotta, M., Lapras, V., Vinet, M., Andrieu, F., Arcamone, J.

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RF Performance of Devices Processed in Low-Temperature Sequential Integration von Mota Frutuoso, T., Sideris, P., Lugo-Alvarez, J., Garros, X., Brunet, L., Fenouille-Beranger, C., Batude, P., Theodorou, C., Ferrari, P., Gaillard, F.

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Influence of Carbon on pBTI Degradation in GaN-on-Si E-Mode MOSc-HEMT von Viey, A. G., Vandendaele, W., Jaud, M.-A., Gerrer, L., Garros, X., Cluzel, J., Martin, S., Krakovinsky, A., Biscarrat, J., Gwoziecki, R., Plissonnier, M., Gaillard, F., Modica, R., Iucolano, F., Meneghini, M., Meneghesso, G., Ghibaudo, G.

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FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration von Fenouillet-Beranger, C., Previtali, B., Batude, P., Nemouchi, F., Cassé, M., Garros, X., Tosti, L., Rambal, N., Lafond, D., Dansas, H., Pasini, L., Brunet, L., Deprat, F., Grégoire, M., Mellier, M., Vinet, M.

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FDSOI devices with thin BOX and ground plane integration for 32 nm node and below von Fenouillet-Beranger, C., Denorme, S., Perreau, P., Buj, C., Faynot, O., Andrieu, F., Tosti, L., Barnola, S., Salvetat, T., Garros, X., Cassé, M., Allain, F., Loubet, N., Pham-Nguyen, L., Deloffre, E., Gros-Jean, M., Beneyton, R., Laviron, C., Marin, M., Leyris, C., Haendler, S., Leverd, F., Gouraud, P., Scheiblin, P., Clement, L., Pantel, R., Deleonibus, S., Skotnicki, T.

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Reliability of ultra-thin buried oxides for multi-VT FDSOI technology von Besnard, G., Garros, X., Nguyen, P., Andrieu, F., Reynaud, P., Van Den Daele, W., Bourdelle, K.K., Schwarzenbach, W., Toffoli, A., Kies, R., Delprat, D., Reimbold, G., Cristoloveanu, S.

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Interface states characterization in heterojunction solar cells from CV– GV measurements and modeling von Garros, X., Reimbold, G., Cluzel, J., Muñoz, D., Ribeyron, P.-J.

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A study of N-induced traps due to a nitrided gate in high-κ/metal gate nMOSFETs and their impact on electron mobility von Cassé, M., Garros, X., Weber, O., Andrieu, F., Reimbold, G., Boulanger, F.

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Performance and reliability of advanced High-K/Metal gate stacks (Invited Paper) von Garros, X., Casse, M., Reimbold, G., Rafik, M., Martin, F., Andrieu, F., Cosnier, V., Boulanger, F.

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Initial and PBTI-induced traps and charges in Hf-based oxides/TiN stacks von Reimbold, G., Mitard, J., Garros, X., Leroux, C., Ghibaudo, G., Martin, F.

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Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond von Andrieu, F, Weber, O, Mazurier, J, Thomas, O, Noel, J.-P, Fenouillet-Béranger, C, Mazellier, J.-P, Perreau, P, Poiroux, T, Morand, Y, Morel, T, Allegret, S, Loup, V, Barnola, S, Martin, F, Damlencourt, J.-F, Servin, I, Cassé, M, Garros, X, Rozeau, O, Jaud, M.-A, Cibrario, G, Cluzel, J, Toffoli, A, Allain, F, Kies, R, Lafond, D, Delaye, V, Tabone, C, Tosti, L, Brévard, L, Gaud, P, Paruchuri, V, Bourdelle, K K, Schwarzenbach, W, Bonnin, O, Nguyen, B.-Y, Doris, B, Bœuf, F, Skotnicki, T, Faynot, O

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Multi-Channel Field-Effect Transistor (MCFET)-Part II: Analysis of Gate Stack and Series Resistance Influence on the MCFET Performance von Bernard, E., Ernst, T., Guillaumot, B., Vulliet, N., Garros, X., Coronel, P., Skotnicki, T., Deleonibus, S., Faynot, O.

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SiON and SiO2/HfSiON gate oxides time dependent dielectric breakdown measurements at nanoscale in ultra high vacuum von DELCROIX, P, BLONKOWSKI, S, GARROS, X, GRAMPEIX, H, GASSILLOUD, R, KOGELSCHATZ, M, RAFIK, M, GOURHANT, O, JEANJEAN, D, BENEYTON, R, ROY, D, FEDERSPIEL, X, MARTIN, F

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High performance 70 nm gate length germanium-on-insulator pMOSFET with high- k/metal gate von Romanjek, K., Hutin, L., Le Royer, C., Pouydebasque, A., Jaud, M.-A., Tabone, C., Augendre, E., Sanchez, L., Hartmann, J.-M., Grampeix, H., Mazzocchi, V., Soliveres, S., Truche, R., Clavelier, L., Scheiblin, P., Garros, X., Reimbold, G., Vinet, M., Boulanger, F., Deleonibus, S.

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Process dependence of BTI reliability in advanced HK MG stacks von Garros, X., Casse, M., Rafik, M., Fenouillet-Béranger, C., Reimbold, G., Martin, F., Wiemer, C., Boulanger, F.

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Understanding of the thermal stability of the hafnium oxide/TiN stack via 2 “high k” and 2 metal deposition techniques von Cosnier, V., Besson, P., Loup, V., Vandroux, L., Minoret, S., Cassé, M., Garros, X., Pedini, J-M., Lhostis, S., Dabertrand, K., Morin, C., Wiemer, C., Perego, M., Fanciulli, M.

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Impact of a HTO/Al2O3 bi-layer blocking oxide in nitride-trap non-volatile memories von BOCQUET, M, MOLAS, G, TOFFOLI, A, DELEONIBUS, S, GHIBAUDO, G, PANANAKAKIS, G, DE SALVO, B, PERNIOLA, L, GARROS, X, BUCKLEY, J, GELY, M, COLONNA, J. P, GRAMPEIX, H, MARTIN, F, VIDAL, V

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MOCVD fluorine free WSix metal gate electrode on high-k dielectric for NMOS technology von GASSILLOUD, R, MARTIN, F, LEROUX, C, HOPSTAKEN, M, GARROS, X, CASSE, M, REIMBOLD, Gilles, BILLON, Thierry, BENSAHEL, Daniel

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Strain sensitivity of gate leakage in strained-SOI nMOSFETs: A benefit for the performance trade-off and a novel way to extract the strain-induced band offset von Rochette, F., Garros, X., Reimbold, G., Andrieu, F., Cassé, M., Mouis, M., Ghibaudo, G., Boulanger, F.

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Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI von Bernard, Emilie, Ernst, T., Guillaumot, B., Vulliet, N., Garros, X., Maffini-Alvaro, V., Coronel, P., Skotnicki, T., Deleonibus, S.

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