Methods and apparatus to implement a boundary scan for shared analog and digital pins von Gangasani, Swathi, Pillai, Prasanth Viswanathan, Sarkar, Vaskar

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METHODS AND APPARATUS TO IMPLEMENT A BOUNDARY SCAN FOR SHARED ANALOG AND DIGITAL PINS von Gangasani, Swathi, Pillai, Prasanth Viswanathan, Sarkar, Vaskar

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Hybrid test compression architecture using multiple codecs for low pin count and high compression devices von GANGASANI SWATHI, SHAH MALAV SHRIKANT, RAVI SRIVATHS

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HYBRID TEST COMPRESSION ARCHITECTURE USING MULTIPLE CODECS FOR LOW PIN COUNT AND HIGH COMPRESSION DEVICES von GANGASANI SWATHI, SHAH MALAV SHRIKANT, RAVI SRIVATHS

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Interruptible non-destructive run-time built-in self-test for field testing von GANGASANI SWATHI, PAREKHJI RUBIN AJIT, ALAMPALLY SRINIVASULU, SAMPATH PADMINI, CHAKRAVARTHY SRINIVASA B S, CHOWDHURY PROHOR

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On-chip seed generation using boolean functions for LFSR re-seeding based logic BIST techniques for low cost field testability von GANGASANI SWATHI, DIVAKARAN DIVYA, PAREKHJI RUBIN AJIT, ALAMPALLY SRINIVASULU, DUTTA AMIT KUMAR, RAVI SRIVATHS

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On-chip seed generation using boolean functions for LFSR re-seeding based logic BIST techniques for low cost field testability von Gangasani, Swathi, Alampally, Srinivasulu, Divakaran, Divya, Parekhji, Rubin Ajit, Dutta, Amit Kumar, Ravi, Srivaths

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INTERRUPTIBLE NON-DESTRUCTIVE RUN-TIME BUILT-IN SELF-TEST FOR FIELD TESTING von GANGASANI SWATHI, PAREKHJI RUBIN AJIT, ALAMPALLY SRINIVASULU, SAMPATH PADMINI, CHAKRAVARTHY SRINIVASA B S, CHOWDHURY PROHOR

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On-Chip Seed Generation Using Boolean Functions for LFSR Re-Seeding Based Logic BIST Techniques for Low Cost Field Testability von GANGASANI SWATHI, DIVAKARAN DIVYA, PAREKHJI RUBIN AJIT, ALAMPALLY SRINIVASULU, DUTTA AMIT KUMAR, RAVI SRIVATHS

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