Global Conflict and the Countours of a New World Order

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LMS-based calibration of an RF digitally controlled oscillator for mobile phones von Staszewski, R.B., Wallberg, J., Chih-Ming Hung, Feygin, G., Entezari, M., Leipold, D.

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Transformation of Pension Systems in the Countries of Eurasian Economic Union von Dyatlov, S A, Feygin, G F, Lebedeva, L F

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Architectural tradeoffs for survivor sequence memory management in Viterbi decoders von Feygin, G., Gulak, P.

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Transformation of Pension Systems in the Countries of Eurasian Economic Union von Dyatlov, S. A., Feygin, G. F., Lebedeva, L. F.

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A 160-MHz analog equalizer for magnetic disk read channels von Kiriaki, S., Viswanathan, T.L., Feygin, G., Staszewski, B., Pierson, R., Krenik, B., De Wit, M., Nagaraj, K.

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A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation von Feygin, G., Nagaraj, K., Chattopadhyay, R., Herrera, R., Papantonopoulos, I., Martin, D., Wu, P., Pavan, S.

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A multiprocessor architecture for Viterbi decoders with linear speedup von Feygin, G., Gulak, P.G., Chow, P.

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A low-cost quad-band single-chip GSM/GPRS radio in 90nm digital CMOS von Muhammad, K., Hung, C.-M., Leipold, D., Mayhugh, T., Elahi, I., Deng, I., Fernando, C., Lee, M.-C., Murphy, T., Wallberg, J.L., Staszewski, R.B., Larson, S., Jung, T., Cruise, P., Roussel, V., Vemulapalli, S.K., Staszewski, R., Eliezer, O.E., Feygin, G., Kunz, K., Maggio, K.

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A 0.8mm2 all-digital SAW-less polar transmitter in 65nm EDGE SoC von Mehta, J., Staszewski, R.B., Eliezer, O., Rezeq, S., Waheed, K., Entezari, M., Feygin, G., Vemulapalli, S., Zoicas, V., Chih-Ming Hung, Barton, N., Bashir, I., Maggio, K., Frechette, M., Meng-Chang Lee, Wallberg, J., Cruise, P., Yanduru, N.

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Generalized cascade Viterbi decoder-a locally connected multiprocessor with linear speed-up von Feygin, G., Gulak, P.G., Chow, P.

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A 24mm2 Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS von Staszewski, R. B., Leipold, D., Eliezer, O., Entezari, M., Muhammad, K., Bashir, I., Hung, C.-M., Wallberg, J., Staszewski, R., Cruise, P., Rezeq, S., Vemulapalli, S., Waheed, K., Barton, N., Lee, M.-C., Fernando, C., Maggio, K., Jung, T., Elahi, I., Larson, S., Murphy, T., Feygin, G., Deng, I., Mayhugh, T., Ho, Y.-C., Low, K.-M., Lin, C., Jaehnig, J., Kerr, J., Mehta, J., Glock, S., Almholt, T., Bhatara, S.

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Minimizing excess code length and VLSI complexity in the multiplication free approximation of arithmetic coding: Data compression von FEYGIN, G, GLEN GULAK, P, CHOW, P

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Mismatch considerations in an RF-DAC design for a digital polar EDGE transmitter von Mehta, J., Staszewski, R. B., Feygin, G., Eliezer, O., Frechette, M., Balsara, P.

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A 160 MHz analog equalizer for magnetic disk read channels von Kiriaki, S., Viswanathan, T.L., Feygin, G., Staszewski, B., Pierson, R., Krenik, B., De Wit, M., Nagaraj, K.

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Minimizing excess code length and VLSI complexity in the multiplication free approximation of arithmetic coding von Feygin, Gennady, Gulak, P.Glenn, Chow, Paul

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Survivor sequence memory management in Viterbi decoders von Feygin, G., Gulak, P.G.

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Implementation of a high speed digital band-pass sigma-delta modulator for a wireless transmitter von Parikh, V.K., Feygin, G., Balsara, P.T., Rezeq, S., Staszewski, R.B., Vemulapalli, S., Eliezer, O.

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Architectural advances in the VLSI implementation of arithmetic coding for binary image compression von Feygin, G., Gulak, P.G., Chow, P.

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RACER: a reconfigurable constraint-length 14 Viterbi decoder von Yeh, Feygin, Chow

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