Instruction scheduling for instruction level parallel processors von Faraboschi, P., Fisher, J.A., Young, C.

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DELI: a new run-time control point von Desoli, G., Mateev, N., Duesterwald, E., Faraboschi, P., Fisher, J.A.

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An Application-Aware Load Balancing Strategy for Network Processors von Ohlendorf, Rainer, Meitinger, Michael, Wild, Thomas, Herkersdorf, Andreas

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The design of a technology platform for custom VLIW embedded processors von Faraboschi, Paolo

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Scalable Shared-Cache Management by Containing Thrashing Workloads von Xie, Yuejian, Loh, Gabriel H.

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Remote Store Programming: A Memory Model for Embedded Multicore von Hoffmann, Henry, Wentzlaff, David, Agarwal, Anant

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Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions von Kluter, Theo, Burri, Samuel, Brisk, Philip, Charbon, Edoardo, Ienne, Paolo

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RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor von Homayoun, Houman, Gupta, Aseem, Veidenbaum, Alex, Sasan (M.A. Makhzan), Avesta, Kurdahi, Fadi, Dutt, Nikil

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Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems von Ferri, Cesare, Wood, Samantha, Moreshet, Tali, Bahar, Iris, Herlihy, Maurice

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HPC-Aware VM Placement in Infrastructure Clouds von Gupta, A., Kale, L. V., Milojicic, D., Faraboschi, P., Balle, S. M.

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Tagged Procedure Calls (TPC): Efficient Runtime Support for Task-Based Parallelism on the Cell Processor von Tzenakis, George, Kapelonis, Konstantinos, Alvanos, Michail, Koukos, Konstantinos, Nikolopoulos, Dimitrios S., Bilas, Angelos

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A VLSI architecture for hierarchical motion estimation von Costa, A., De Gloria, A., Faraboschi, P., Passaggio, F.

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Offload – Automating Code Migration to Heterogeneous Multicore Systems von Cooper, Pete, Dolinsky, Uwe, Donaldson, Alastair F., Richards, Andrew, Riley, Colin, Russell, George

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Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching von Grannaes, Marius, Jahre, Magnus, Natvig, Lasse

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Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors von Carpenter, Paul M., Ramirez, Alex, Ayguadé, Eduard

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Trace-Based Data Layout Optimizations for Multi-core Processors von Golovanevsky, Olga, Dayan, Alon, Zaks, Ayal, Edelsohn, David

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SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs von Srikantaiah, Shekhar, Kandemir, Mahmut

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DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems von Jahre, Magnus, Grannaes, Marius, Natvig, Lasse

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Clustered Boltzmann Machines: Massively parallel architectures for constrained optimization problems von De Gloria, A, Faraboschi, P, Olivieri, M

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A boltzmann machine approach to code optimization von De Gloria, A., Faraboschi, P.

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