SimFlex: Statistical Sampling of Computer System Simulation von Wenisch, T.F., Wunderlich, R.E., Ferdman, M., Ailamaki, A., Falsafi, B., Hoe, J.C.

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Power-Aware Computer Systems: First International Workshop, PACS 2000 Cambridge, MA, USA, November 12, 2000 Revised Papers von Falsafi, B, Vijaykumar, T. N

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Power-Aware Computer Systems: Second International Workshop, PACS 2002 Cambridge, MA, USA, February 2, 2002, Revised Papers von Falsafi, Babak, Vijaykumar, T. N

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Energy-efficient server clusters von ELNOZAHY, E. N, KISTLER, Michael, RAJAMONY, Ramakrishnan

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Toward Dark Silicon in Servers von Hardavellas, N., Ferdman, M., Falsafi, B., Ailamaki, A.

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A case for asymmetric-cell cache memories von Moshovos, A., Falsafi, B., Najm, F.N., Azizi, N.

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Speculative sequential consistency with little custom storage von Gniady, C., Falsafi, B.

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Dead-block prediction & dead-block correlating prefetchers von An-Chow Lai, Fide, C., Falsafi, B.

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Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays von Cantin, J.F., Smith, J.E., Lipasti, M.H., Moshovos, A., Falsafi, B.

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Flexible Hardware Acceleration for Instruction-Grain Lifeguards von Chen, S., Kozuch, M., Gibbons, P.B., Ryan, M., Strigkos, T., Mowry, T.C., Ruwase, O., Vlachos, E., Falsafi, B., Ramachandran, V.

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Power Consumption Breakdown on a Modern Laptop von Mahesri, Aqeel, Vardhan, Vibhore

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Reducing leakage in a high-performance deep-submicron instruction cache von Powell, M., Se-Hyun Yang, Falsafi, B., Roy, K., Vijaykumar, N.

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Fingerprinting: bounding soft-error-detection latency and bandwidth von Smolens, J.C., Gold, B.T., Kim, J., Falsafi, B., Hoe, J.C., Nowatryk, A.G.

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Optimizing Data-Center TCO with Scale-Out Processors von Grot, B., Hardy, D., Lotfi-Kamran, P., Falsafi, B., Nicopoulos, C., Sazeides, Y.

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Cuckoo directory: A scalable directory for many-core systems von Ferdman, M, Lotfi-Kamran, P, Balet, K, Falsafi, B

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Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding von Jangwoo Kim, Hardavellas, N., Ken Mai, Falsafi, B., Hoe, J.C.

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Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures von Smolens, Jared C., Kim, Jangwoo, Hoe, James C., Falsafi, Babak

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The synergy between power-aware memory systems and processor voltage scaling von XIAOBO FAN, ELLIS, Carla S, LEBECK, Alvin R

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Exploiting choice in resizable cache design to optimize deep-submicron processor energy-delay von Se-Hyun Yang, Powell, M.D., Falsafi, B., Vijaykumar, T.N.

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Energy consumption in mobile devices: Why future systems need requirements-aware energy scale-down von MAYO, Robert N, RANGANATHAN, Parthasarathy

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