Shared resource aware scheduling on power-constrained tiled many-core processors von Jha, Sudhanshu Shekhar, Heirman, Wim, Falcón, Ayose, Tubella, Jordi, González, Antonio, Eeckhout, Lieven

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Better branch prediction through prophet/critic hybrids von Falcon, A., Stark, J., Ramirez, A., Lai, K., Valero, M.

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DIA: A Complexity-Effective Decoding Architecture von Santana, O.J., Falcon, A., Ramirez, A., Valero, M.

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Shared resource aware scheduling on power-constrained tiled many-core processors von Jha, Sudhanshu Shekhar, Heirman, Wim, Falcón Samper, Ayose Jesús, Tubella Murgadas, Jordi, González Colás, Antonio María, Eeckhout, Lieven

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A low-complexity, high-performance fetch unit for simultaneous multithreading processors von Falcon, A., Ramirez, A., Valero, V.

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A complexity-effective simultaneous multithreading architecture von Acosta, C., Falcon, A., Ramirez, A., Valero, M.

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Prophet/critic hybrid branch prediction von Falcon, A., Stark, J., Ramirez, A., Lai, K., Valero, M.

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Chrysso: an integrated power manager for constrained many-core processors von Jha, Sudhanshu Shekhar, Heirman, Wim, Falcón Samper, Ayose Jesus, Carlson, Trevor E, Van Craeynest, Kenzo, Tubella Murgadas, Jordi, González Colás, Antonio María, Eeckhout, Lieven

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Author retrospective for "Software trace cache" von Ramírez Bellido, Alejandro, Falcón Samper, Ayose Jesus, Santana Jaria, Oliverio J, Valero Cortés, Mateo

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Effective instruction prefetching via fetch prestaging von Falcon, A., Ramirez, A., Valero, M.

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Maximizing multithreaded multicore architectures through thread migrations von Acosta Ojeda, Carmelo Alexis, Cazorla Almeida, Francisco Javier, Santana Jaria, Oliverio J, Falcón Samper, Ayose Jesús, Ramírez Bellido, Alejandro, Valero Cortés, Mateo

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