Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance von Kumar, Rakesh, Tullsen, Dean M., Ranganathan, Parthasarathy, Jouppi, Norman P., Farkas, Keith I.

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Guest Editors' Introduction: Virtual Machines von Farkas, Keith I., Narayanaswami, Chandra, Nieh, Jason

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Leendert van Doorn and Jörg Brakensiek on Virtual Machines [Interview] von Farkas, Keith I.

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Guest Editors' Introduction: Building a Sensor-Rich World von Borriello, Gaetano, Farkas, Keith I., Reynolds, Franklin, Zhao, Feng

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The multicluster architecture: reducing cycle time through partitioning von Farkas, K.I., Chow, P., Jouppi, N.P., Vranesic, Z.

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The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays von Hrishikesh, M. S., Burger, Doug, Jouppi, Norman P., Keckler, Stephen W., Farkas, Keith I., Shivakumar, Premkishore

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Dealing with Scale and Adaptation of Global Web Services Management von Vambenepe, William, Thompson, Carol, Talwar, Vanish, Rafaeli, Sandro, Murray, Bryan, Milojicic, Dejan, Iyer, Subu, Farkas, Keith I, Arlitt, Martin

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Energy-Driven Statistical Sampling: Detecting Software Hotspots von Chang, Fay, Farkas, Keith I., Ranganathan, Parthasarathy

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Leendert van Doorn and JAPGrg Brakensiek on Virtual Machines von Farkas, Keith I

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Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction von Kumar, Rakesh, Farkas, Keith I., Jouppi, Norman P., Ranganathan, Parthasarathy, Tullsen, Dean M.

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Memory-system design considerations for dynamically-scheduled processors von Farkas, Keith I., Chow, Paul, Jouppi, Norman P., Vranesic, Zvonko

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Disappearing hardware [ubiquitous computing] von Want, R., Pering, T., Borriello, G., Farkas, K.I.

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The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays von Hrishikesh, M. S., Burger, Doug, Jouppi, Norman P., Keckler, Stephen W., Farkas, Keith I., Shivakumar, Premkishore

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The multicluster architecture: Reducing processor cycle time through partitioning von Farkas, Keith I, Chow, Paul, Jouppi, Norman P, Vranesic, Zvonko

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The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays von Hrishikesh, M.S., Jouppi, N.P., Farkas, K.I., Burger, D., Keckler, S.W., Shivakumar, P.

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Memory-system design considerations for dynamically-scheduled processors von Farkas, Keith I., Chow, Paul, Jouppi, Norman P., Vranesic, Zvonko

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Quantifying the energy consumption of a pocket computer and a Java virtual machine von Farkas, Keith I., Flinn, Jason, Back, Godmar, Grunwald, Dirk, Anderson, Jennifer M.

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Itsy: stretching the bounds of mobile computing von Hamburgen, W.R., Wallach, D.A., Viredaz, M.A., Brakmo, L.S., Waldspurger, C.A., Bartlett, J.F., Mann, T., Farkas, K.I.

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Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance von Kumar, Rakesh, Tullsen, Dean M., Ranganathan, Parthasarathy, Jouppi, Norman P., Farkas, Keith I.

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Quantifying the energy consumption of a pocket computer and a Java virtual machine von Farkas, Keith I, Flinn, Jason, Back, Godmar, Grunwald, Dirk, Anderson, Jennifer M

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