Optimization of fins used in electronic packaging von Eu Ong, Kang, Oon Lee, Kor, Seetharamu, K.N, Azid, I.A, Quadir, G.A, Zainal, Z.A, Joo Goh, Teck

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Study of Dynamic Warpage of Flip Chip Packages under Temperature Reflow von Chee Kan Lee, Wei Keat Loh, Kang Eu Ong, Chin, I.

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Solder Joint Reliability Performance of Flip Chip Molded Ball Grid Array (BGA) Package for Network/Communication Application von Ong Kang Eu, Too Seong Ling, Loh Wei Keat, Peralta, C., Ong LayLing, Chan Choi Keng, Yap Eng Hooi

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Thermal analysis of embedded chip von Lee Pik San, Ong Kang Eu, Azid, I. A.

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Solder paramater sensitivity for Package-on-Package (POP) on fatigue life prediction von Lim Han Bin, Ong Kang Eu, Azid, I. A.

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The correlation of package coplanarity and reflow warpage to SMT von Lee Yung Hsiang, Ong Kang Eu, Loh Wei Keat, Wong Shaw Fong, Gill, Paramjeet S, Tan Kah Kee

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Solder Joint Reliability (SJR) Study of Integrated Heat Spreader (IHS) Packages von Shaw Fong Wong, Wei Keat Loh, Kang Eu Ong, Yung Hsiang Lee, Huey Ling Lew, Seok Ling Lee

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Application of Artificial Neural Network for Fatigue Life Prediction von Quadir, Ghulam Abdul, Eu, Ong Kang, Azid, Ishak Abdul, Oon, Lee Kor, Seetharamu, K.N.

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LOWER IC PACKAGE STRUCTURE FOR COUPLING WITH AN UPPER IC PACKAGE TO FORM A PACKAGE-ON-PACKAGE (PoP) ASSEMBLY AND PoP ASSEMBLY INCLUDING SUCH A LOWER IC PACKAGE STRUCTURE von Wong, Shaw Fong, Wong, AU Seong, Loh, Wei Keat P, Ong, Kang Eu

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STIFFENER FOR A PACKAGE SUBSTRATE von Kong, Jackson Chung Peng, Lim, Seok Ling, Ong, Jenny Shio Yin, Ong, Kang Eu, Chea, Bok Eng

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CHIP CARRIER HAVING VARIABLY-SIZED PADS von WEI CHUNG Lee, LAM Chun Mun, LOKE Mun Leong, WONG Chee Ling, ONG Kang Eu

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Flip chip assembly process for ultra thin substrate and package on package assembly von LIM SIH FEI, LOKE MUN LEONG, ONG KANG EU, RUDGE A. VETHANAYAGAM, MONG WENG KHOON, LIM BOK SIM, ONG TEAN WEE

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FLIP CHIP ASSEMBLY PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY von LIM SIH FEI, LOKE MUN LEONG, ONG KANG EU, RUDGE A. VETHANAYAGAM, MONG WENG KHOON, LIM BOK SIM, ONG TEAN WEE

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LOWER IC PACKAGE STRUCTURE FOR COUPLING WITH AN UPPER IC PACKAGE TO FORM A PACKAGE-ON-PACKAGE (POP) ASSEMBLY AND POP ASSEMBLY INCLUDING SUCH A LOWER IC PACKAGE STRUCTURE von WONG, SHAW FONG, LOH, WEI KEAT, WONG, AU SEONG, ONG, KANG EU

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LOWER IC PACKAGE STRUCTURE FOR COUPLING WITH AN UPPER IC PACKAGE TO FORM A PACKAGE-ON-PACKAGE (POP) ASSEMBLY AND POP ASSEMBLY INCLUDING SUCH A LOWER IC PACKAGE STRUCTURE von WONG, SHAW FONG, LOH, WEI KEAT, WONG, AU SEONG, ONG, KANG EU

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Lower IC Package Structure for Coupling with an Upper IC Package to Form a Package-On-Package (PoP) Assembly and PoP Assembly Including Such a Lower IC Package Structure von WONG AU SEONG, ONG KANG EU, WONG SHAW FONG, LOH WEI KEAT

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Flip chip assembly process for ultra thin substrate and package on package assembly von LIM SIH FEI, LOKE MUN LEONG, ONG KANG EU, RUDGE A. VETHANAYAGAM, MONG WENG KHOON, LIM BOK SIM, ONE TEAN WEE

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Lower ic package structure for coupling with an upper ic package to form a package-on-package (pop) assembly and pop assembly including such a lower ic package structure von WONG, SHAW FONG, LOH, WEI KEAT, WONG, AU SEONG, ONG, KANG EU

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FLIP CHIP ASSEMBLY PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY von LOKE, MUN LEONG, MONG, WENG KHOON, ONG, TEAN WEE, LIM, BOK SIM, RUDGE, A VETHANAYAGAM, ONG, KANG EU, LIM, SIH FEI

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Flip chip assembly process for ultra thin substrate and package on package assembly von Mong, Weng Khoon, Rudge, A. Vethanayagam, Lim, Bok Sim, Loke, Mun Leong, Ong, Kang Eu, Lim, Sih Fei, Ong, Tean Wee

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