Compact Design of Low Power Standard Ternary Inverter Based on OFF-State Current Mechanism Using Nano-CMOS Technology von Sunhae Shin, Jang, Esan, Jae Won Jeong, Byung-Gook Park, Kyung Rok Kim

Volltext

Low Leakage III-V/Ge CMOS FinFET Design for High-Performance Logic Applications with High-κ Spacer Technology von Esan Jang, Sunhae Shin, Jae Won Jeong, Kyung Rok Kim

Volltext

Low Leakage III-V/Ge CMOS FinFET Design for High-Performance Logic Applications with High-k Spacer Technology von Jang, Esan, Shin, Sunhae, Jeong, Jae Won, Kim, Kyung Rok

Volltext

Gate induced drain leakage reduction with analysis of gate fringing field effect on high-κ/metal gate CMOS technology von Jang, Esan, Shin, Sunhae, Jung, Jae Won, Kim, Kyung Rok

Volltext

Low Leakage III-V/Ge CMOS FinFET Design for High-Performance Logic Applications with High-κ Spacer Technology von Jang, Esan, Shin, Sunhae, Jeong, Jae Won, Kim, Kyung Rok

Volltext