Efficient Microarchitectural Vulnerabilities Prediction Using Boosted Regression Trees and Patient Rule Inductions von Li, Bin, Duan, Lide, Peng, Lu

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Improving the SSD Performance by Exploiting Request Characteristics and Internal Parallelism von Mao, Bo, Wu, Suzhen, Duan, Lide

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Predicting Architectural Vulnerability on Multithreaded Processors under Resource Contention and Sharing von Duan, Lide, Peng, Lu, Li, Bin

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Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metrics von Lide Duan, Bin Li, Lu Peng

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iCELIA: A Full-Stack Framework for STT-MRAM-Based Deep Learning Acceleration von Yan, Hao, Cherian, Hebin R., Ahn, Ethan C., Qian, Xuehai, Duan, Lide

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Expediating IP lookups with reduced power via TBM and SST supernode caching von Zhang, Ying, Peng, Lu, Lu, Wencheng, Duan, Lide, Rai, Suresh

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Mitigating and Tolerating Read Disturbance in STT-MRAM-Based Main Memory via Device and Architecture Innovations von Haj Aboutalebi, Armin, Ahn, Ethan C., Mao, Bo, Wu, Suzhen, Duan, Lide

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Comprehensive and Efficient Design Parameter Selection for Soft Error Resilient Processors via Universal Rules von Duan, Lide, Zhang, Ying, Li, Bin, Peng, Lu

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Computer comparisons in the presence of performance variation von IRVING, Samuel, LI, Bin, CHEN, Shaoming, PENG, Lu, ZHANG, Weihua, DUAN, Lide

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FlowPaP and FlowReR: Improving Energy Efficiency and Performance for STT-MRAM-Based Handheld Devices under Read Disturbance von Yan, Hao, Jiang, Lei, Duan, Lide, Lin, Wei-Ming, John, Eugene

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Cross-architecture prediction based scheduling for energy efficient execution on single-ISA heterogeneous chip-multiprocessors von Zhang, Ying, Duan, Lide, Li, Bin, Peng, Lu, Sadagopan, Srinivasan

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Design configuration selection for hard-error reliable processors via statistical rules von Zhang, Ying, Duan, Lide, Li, Bin, Peng, Lu, Fu, Xin

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PROCESSING UNIT FOR MEMORY AND ACCESS DETECTION METHOD THEREOF von DUAN, LIDE, ZHANG, SHIJIAN

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COMPUTING DEVICE AND METHOD FOR THE SAME von DUAN, LIDE, ZHANG, SHIJIAN

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PROCESSOR AND ATTACK DETECTION METHOD THEREOF von DUAN, LIDE, ZHANG, SHIJIAN

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Universal rules guided design parameter selection for soft error resilient processors von Lide Duan, Ying Zhang, Bin Li, Lu Peng

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Optimal microarchitectural design configuration selection for processor hard-error reliability von Ying Zhang, Lide Duan, Bin Li, Lu Peng

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Two-level soft error vulnerability prediction on SMT/CMP architectures von Lide Duan, Lu Peng, Bin Li

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Power Efficient IP Lookup with Supernode Caching von Lu Peng, Wencheng Lu, Lide Duan

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DATA PROCESSING METHOD AND DATA PROCESSING ACCELERATOR SYSTEM von Zhang, Shijian, Duan, Lide, Zheng, Hongzhong

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