Pi-Gate SOI MOSFET von Jong-Tae Park, Colinge, J.-P., Diaz, C.H.

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An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling von Diaz, C.H., Hun-Jan Tao, Yao-Ching Ku, Yen, A., Young, K.

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Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design von Kleveland, B., Diaz, C.H., Vook, D., Madden, L., Lee, T.H., Wong, S.S.

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Leakage scaling in deep submicron CMOS for SoC von Yo-Sheng Lin, Chung-Cheng Wu, Chih-Sheng Chang, Rong-Ping Yang, Wei-Ming Chen, Jhon-Jhy Liaw, Diaz, C.H.

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Transistor-and Circuit-Design Optimization for Low-Power CMOS von Mi-Chang Chang, Chih-Sheng Chang, Chih-Ping Chao, Ken-Ichi Goto, Meikei Ieong, Lee-Chung Lu, Diaz, C.H.

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CMOS technology for MS/RF SoC von Diaz, C.H., Tang, D.D., Sun, J.Y.-C.

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Interface induced uphill diffusion of boron: an effective approach for ultrashallow junction von Howard Chih-Hao Wang, Chih-Chiang Wang, Chih-Sheng Chang, Tahui Wang, Griffin, P.B., Diaz, C.H.

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A Millisecond-Anneal-Assisted Selective Fully Silicided (FUSI) Gate Process von Da-Wen Lin, Wang, M., Ming-Lung Cheng, Yi-Ming Sheu, Tarng, B., Che-Min Chu, Chun-Wen Nieh, Chia-Ping Lo, Wen-Chi Tsai, Lin, R., Shyh-Wei Wang, Kuan-Lun Cheng, Chii-Ming Wu, Ming-Ta Lei, Chung-Cheng Wu, Diaz, C.H., Ming-Jer Chen

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Separation of channel backscattering coefficients in nanoscale MOSFETs von Ming-Jer Chen, Huan-Tsung Huang, Yi-Chin Chou, Rong-Ting Chen, Yin-Ta Tseng, Po-Nien Chen, Diaz, C.H.

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MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8 nm) von Chang-Hoon Choi, Jung-Suk Goo, Tae-Young Oh, Zhiping Yu, Dutton, R.W., Bayoumi, A., Min Cao, Voorde, P.V., Vook, D., Diaz, C.H.

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Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era von Diaz, C.H., Mi-Chang Chang, Tong-Chern Ong, Sun, J.Y.-C.

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AlxIn1−xAsySb1−y alloys lattice matched to InAs(100) grown by molecular beam epitaxy von Rojas-Ramirez, J.S., Wang, S., Contreras-Guerrero, R., Caro, M., Bhatnagar, K., Holland, M., Oxland, R., Doornbos, G., Passlack, M., Diaz, C.H., Droopad, R.

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High crystalline quality Ge grown by MOCVD inside narrow shallow trench isolation defined on Si(001) substrates von Vellianitis, G., van Dal, M.J.H., Duriez, B., Lee, T.L., Passlack, M., Wann, C.H., Diaz, C.H.

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Al In1−As Sb1− alloys lattice matched to InAs(1 0 0) grown by molecular beam epitaxy von Rojas-Ramirez, J.S., Wang, S., Contreras-Guerrero, R., Caro, M., Bhatnagar, K., Holland, M., Oxland, R., Doornbos, G., Passlack, M., Diaz, C.H., Droopad, R.

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Correction to "exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design" von Kleveland, B., Diaz, C.H., Vook, D., Madden, L., Lee, T.H., Wong, S.S.

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Hot carrier reliability improvement by utilizing phosphorus transient enhanced diffusion for input/output devices of deep submicron CMOS technology von Wang, H.H.-C., Diaz, C.H., Boon-Khim Liew, Sun, J.Y.-C., Tahui Wang

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Arsenic/phosphorus LDD optimization by taking advantage of phosphorus transient enhanced diffusion for high voltage input/output CMOS devices von Wang, H.C.-H., Chih-Chiang Wang, Diaz, C.H., Boon-Khim Liew, Sun, J.Y.-C., Tahui Wang

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Growth of heterostructures on InAs for high mobility device applications von Contreras-Guerrero, R., Wang, S., Edirisooriya, M., Priyantha, W., Rojas-Ramirez, J.S., Bhuwalka, K., Doornbos, G., Holland, M., Oxland, R., Vellianitis, G., Van Dal, M., Duriez, B., Passlack, M., Diaz, C.H., Droopad, R.

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MOVPE-grown InAs/AlAs0.16Sb0.84/InAs and InAs/AlAs0.16Sb0.84/GaSb heterostructures von Ramvall, P., Wang, C.H., Astromskas, G., Vellianitis, G., Holland, M., Droopad, R., Samuelson, L., Wernersson, L.E., Passlack, M., Diaz, C.H.

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MOVPE-grownInAs/AlAs0.16Sb0.84/InAs and InAs/AlAs0.16Sb0.84/GaSb heterostructures von Ramvall, Peter, Wang, C.H., Astromskas, Gvidas, Vellianitis, Georgios, Holland, Martin, Droopad, Ravi, Samuelson, Lars, Wernersson, Lars-Erik, Paslack, Matthias, Diaz, C.H.

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