A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor von Hwa-Joon Oh, Mueller, S.M., Jacobi, C., Tran, K.D., Cottier, S.R., Michael, B.W., Nishikawa, H., Totsuka, Y., Namatame, T., Yano, N., Machida, T., Dhong, S.H.

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Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor von Warnock, J., Wendel, D., Aipperspach, T., Behnen, E., Cordes, R.A., Dhong, S.H., Hirairi, K., Murakami, H., Onishi, S., Pham, D.C., Pille, J., Posluszny, S.D., Takahashi, O., Huajun Wen

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Power-conscious design of the Cell processor's synergistic processor element von Takahashi, O., Cottier, S., Dhong, S.H., Flachs, B., Silberman, J.

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Designing for a gigahertz [guTS integer processor] von Hofstee, H.P., Sang H. Dhong, Meltzer, D., Nowka, K.J., Silberman, J.A., Burns, J.I., Posluszny, S.D., Takahashi, O.

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The microarchitecture of the synergistic processor for a cell processor von Flachs, B., Asano, S., Dhong, S.H., Hofstee, H.P., Gervais, G., Roy Kim, Le, T., Peichun Liu, Leenstra, J., Liberty, J., Michael, B., Hwa-Joon Oh, Mueller, S.M., Takahashi, O., Hatakeyama, A., Watanabe, Y., Yano, N., Brokenshire, D.A., Peyravian, M., Vandung To, Iwata, E.

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Structural effects on a submicron trench process von DAEJE CHIN, DHONG, S. H, LONG, G. J

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Low-power design approach of 11FO4 256-Kbyte embedded SRAM for the synergistic processor element of a Cell processor von Asano, T., Silberman, J., Dhong, S.H., Takahashi, O., White, M., Cottier, S., Nakazato, T., Kawasumi, A., Yoshihara, H.

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A 14-NS 4-MB CMOS DRAM WITH 300-MW ACTIVE POWER von KIRIHATA, T, DHONG, SH, KITAMURA, K, SUNAGA, T, KATAYAMA, Y, SCHEUERLEIN, RE, SATOH, A, SAKAUE, Y, TOBIMATSU, K, HOSOKAWA, K, SAITOH, T, YOSHIKAWA, T, HASHIMOTO, H, KAZUSAWA, M

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A 4.8GHz fully pipelined embedded SRAM in the streaming processor of a CELL processor von Dhong, S.H., Takahashi, O., White, M., Asano, T., Nakazato, T., Silberman, J., Kawasumi, A., Yoshihara, H.

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1-GHz fully pipelined 3.7-ns address access time 8 k x 1024 embedded synchronous DRAM macro von Takahashi, Osamu, Dhong, Sang H, Ohkubo, Manabu, Onishi, Shohji, Dennard, Robert H, Hannon, Robert, Crowder, Scott, Iyer, Subramanian S, Wordeman, Matthew R, Davari, Bijan, Weinberger, William B, Aoki, Naoaki

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1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro von Takahashi, O, Dhong, S.H, Ohkubo, M, Onishi, S, Dennard, R.H, Hannon, R, Crowder, S, Iyer, S.S, Wordeman, M.R, Davari, B, Weinberger, W.B, Aoki, N

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SENSE AMPLIFIER BASED FLIP-FLOP von MANDAL GURUPADA, DHONG SANG H

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Reducing power requirements of a multiple core processor von FLACHS BRIAN K, GERVAIS GILLES, DHONG SANG H, TAMURA TETSUJI

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Designing for a gigahertz - guTS integer processor von Hofstee, H P, Dhong, Sang H, Meltzer, D, Nowka, K J, Silberman, J A, Burns, J I, Posluszny, S D, Takahashi, O

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A variable precharge voltage sensing von Eirihata, T., Dhong, S.H., Terman, L.M., Sunaga, T., Taira, Y.

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Reducing Power Requirements of a Multiple Core Processor von FLACHS BRIAN K, GERVAIS GILLES, DHONG SANG H, TAMURA TETSUJI

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Dynamic random access memory (DRAM) cells and methods for fabricating the same von MANDAL GURUPADA, DHONG SANG H, GOO JUNG-SUK, CHO HYUN-JIN

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DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELLS AND METHODS FOR FABRICATING THE SAME von MANDAL GURUPADA, DHONG SANG H, GOO JUNG-SUK, CHO HYUN-JIN

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Sidewall spacer technology for MOS and bipolar devices von DHONG, S. H, PETRILLO, E. J

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Design and characteristics of a lightly doped drain (LDD) device fabricated with self-aligned titanium disilicide von Fang-Shi J. Lai, Jack Yuan-Chen Sun, Dhong, S.H.

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