A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor von Hwa-Joon Oh, Mueller, S.M., Jacobi, C., Tran, K.D., Cottier, S.R., Michael, B.W., Nishikawa, H., Totsuka, Y., Namatame, T., Yano, N., Machida, T., Dhong, S.H.

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Power-conscious design of the Cell processor's synergistic processor element von Takahashi, O., Cottier, S., Dhong, S.H., Flachs, B., Silberman, J.

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Low-power design approach of 11FO4 256-Kbyte embedded SRAM for the synergistic processor element of a Cell processor von Asano, T., Silberman, J., Dhong, S.H., Takahashi, O., White, M., Cottier, S., Nakazato, T., Kawasumi, A., Yoshihara, H.

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The microarchitecture of the synergistic processor for a cell processor von Flachs, B., Asano, S., Dhong, S.H., Hofstee, H.P., Gervais, G., Roy Kim, Le, T., Peichun Liu, Leenstra, J., Liberty, J., Michael, B., Hwa-Joon Oh, Mueller, S.M., Takahashi, O., Hatakeyama, A., Watanabe, Y., Yano, N., Brokenshire, D.A., Peyravian, M., Vandung To, Iwata, E.

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A pulsed sensing scheme with a limited bit-line swing von Scheuerlein, R.E., Katayama, Y., Kirihata, T., Sakaue, Y., Satoh, A., Sunaga, T., Yoshikawa, T., Kitamura, K., Dhong, S.H.

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Sidewall spacer technology for MOS and bipolar devices von DHONG, S. H, PETRILLO, E. J

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The circuit design of the synergistic processor element of a CELL processor von Takahashi, O., Cook, R., Cottier, S., Dhong, S. H., Flachs, B., Hirairi, K., Kawasumi, A., Murakami, H., Noro, H., Oh, H., Onish, S., Pille, J., Silberman, J.

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A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing von Lu, N.C.-C., Bronner, G.B., Kitamura, K., Scheuerlein, R.E., Henkels, W.H., Dhong, S.H., Katayama, Y., Kirihata, T., Niijima, H., Franch, R.L., Wang, W., Nishiwaki, M., Pesavento, F.L., Rajeevakumar, T.V., Sakaue, Y., Suzuki, Y., Iguchi, Y., Yano, E.

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A symmetrical three-junction superconducting quantum interference device von DHONG, S. H, JEWETT, R. E, SPARGO, J. W, VAN DUZER, T

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Structural effects on a submicron trench process von DAEJE CHIN, DHONG, S. H, LONG, G. J

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A streaming processing unit for a CELL processor von Flachs, B., Asano, S., Dhong, S.H., Hotstee, P., Gervais, G., Kim, R., Le, T., Liu, P., Leenstra, J., Liberty, J., Michael, B., Oh, H., Mueller, S.M., Takahashi, O., Hatakeyama, A., Watanabe, Y., Yano, N.

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A variable precharge voltage sensing von Eirihata, T., Dhong, S.H., Terman, L.M., Sunaga, T., Taira, Y.

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Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor von Warnock, J., Wendel, D., Aipperspach, T., Behnen, E., Cordes, R.A., Dhong, S.H., Hirairi, K., Murakami, H., Onishi, S., Pham, D.C., Pille, J., Posluszny, S.D., Takahashi, O., Huajun Wen

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A large VDS data retention test pattern for DRAM's von FRANCH, R. L, DHONG, S. H, SCHEUERLEIN, R. E

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A 14-ns 4-Mb CMOS DRAM with 300-mW active power von KIRIHATA, T, DHONG, S. H, SAITOH, T, YOSHIKAWA, T, HASHIMOTO, H, KAZUSAWA, M, KITAMURA, K, SUNAGA, T, KATAYAMA, Y, SCHEUERLEIN, R. E, SATOH, A, SAKAUE, Y, TOBIMATSU, K, HOSOKAWA, K

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Design and characteristics of a lightly doped drain (LDD) device fabricated with self-aligned titanium disilicide von Fang-Shi J. Lai, Jack Yuan-Chen Sun, Dhong, S.H.

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The circuits and physical design of the synergistic processor element of a CELL processor von Takahashi, O., Cook, R., Cottier, S., Dhong, S.H., Flachs, B., Hirairi, K., Kawasumi, A., Murakami, H., Noro, H., Oh, H., Onishi, S., Pille, J., Silberman, J., Yong, S.

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Cell Broadband Engine Processor Design Methodology von Takahashi, O., Behnen, E., Cottier, S.R., Coulman, P., Dhong, S.H., Flachs, B., Hofstee, P., Johnson, C.J., Posluszny, S.

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A Josephson dc-powered latch von Dhong, Sang H., Gheewala, Tushar

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Minimum-width control-current pulse for Josephson logic gates von Dhong, S.H., Van Duzer, T.

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