Environment for the analysis of functional self-test quality in digital systems von Ubar, Raimund, Kostin, Sergei, Kruus, Helena, Aarna, Margit, Devadze, Sergei

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Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures von Aleksejev, Igor, Devadze, Sergei, Jutman, Artur, Shibin, Konstantin

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Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra von Kõusaar, Jaak, Ubar, Raimund, Devadze, Sergei, Raik, Jaan

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Functional self-test of high-performance pipe-lined signal processing architectures von Gorev, Maksim, Ubar, Raimund, Ellervee, Peeter, Devadze, Sergei, Raik, Jaan, Min, Mart

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FPGA-based synthetic instrumentation for board test von Aleksejev, I., Jutman, A., Devadze, S., Odintsov, S., Wenzel, T.

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Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis von Devadze, Sergei, Nielsen, Christine Elizabeth, Mihhailov, Dmitri, Ellervee, Peeter

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Design, Verification and Application of IEEE 1687 von Ghani Zadegan, Farrokh, Larsson, Erik, Jutman, Artur, Devadze, Sergei, Krenz-Baath, René

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Parallel X-fault simulation with critical path tracing technique von Ubar, Raimund, Devadze, Sergei, Raik, Jaan, Jutman, Artur

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On-Chip Sensors Data Collection and Analysis for SoC Health Management von Shibin, Konstantin, Jenihhin, Maksim, Jutman, Artur, Devadze, Sergei, Tsertov, Anton

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Open-Source JTAG Simulator Bundle for Labs von Shibin, Konstantin, Devadze, Sergei, Rosin, Vjatseslav, Jutman, Artur, Ubar, Raimund

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HLS-based Optimization of Tau Triggering Algorithm for LHC: a case study von Cherezova, Natalia, Mihhailov, Dmitri, Devadze, Sergei, Jutman, Artur

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Fast extended test access via JTAG and FPGAs von Devadze, S., Jutman, A., Aleksejev, I., Ubar, R.

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Automatic SoC Level Test Path Synthesis Based on Partial Functional Models von Tsertov, A., Ubar, R., Jutman, A., Devadze, S.

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Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs von Raik, Jaan, Ubar, Raimund, Devadze, Sergei, Jutman, Artur

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Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis von Devadze, Sergei, Nielsen, Christine Elizabeth, Mihhailov, Dmitri, Ellervee, Peeter

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On-Chip Sensors Data Collection and Analysis for SoC Health Management von Shibin, Konstantin, Jenihhin, Maksim, Jutman, Artur, Devadze, Sergei, Tsertov, Anton

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On in-system programming of non-volatile memories von Tsertov, Anton, Devadze, Sergei, Jutman, Artur, Jasnetski, Artjom

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Embedded synthetic instruments for Board-Level testing von Jutman, A., Devadze, S., Aleksejev, I., Wenzel, T.

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SoC and Board Modeling for Processor-Centric Board Testing von Tsertov, A., Ubar, R., Jutman, A., Devadze, S.

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System and method for optimized board test and configuration von DEVADZE SERGEI, ALEKSEJEV IGOR, WENZEL THOMAS, SHIBIN KONSTANTIN, JUTMAN ARTUR

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