Sex Steroids, Bone Mass and Bone Turnover Markers in Asian Indians von Desai, M.P, Venkat, K, Prakash, K. V. Bhanu, Khatkhatay, M

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The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance von Mohapatra, N.R., Desai, M.P., Narendra, S.G., Rao, V.R.

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Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors von Mohapatra, N.R., Desai, M.P., Narendra, S.G., Ramgopal Rao, V.

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The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performance von Narasimhulu, K., Desai, M.P., Narendra, S.G., Rao, V.R.

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Silicon film thickness optimization for SOI-DTMOS from circuit performance considerations von Anand, B., Desai, M.P., Rao, V.R.

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Silicon film thickness considerations in SOI-DTMOS von Sivaram, P., Anand, B., Desai, M.P.

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Bottleneck Identification Techniques Leading to Simplified Performance Models for Efficient Design Space Exploration in VLSI Memory Systems von Hazari, G., Desai, M.P., Srinivas, G.

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Learning based address mapping for improving the performance of memory subsystems von Kumar, P., Desai, M.P.

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On the Impact of Address Space Assignment on Performance in Systems-on-Chip von Hazari, G., Desai, M.P., Kasture, H.

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Variance reduction in Monte Carlo capacitance extraction von Batterywala, S.H., Desai, M.P.

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The realization of finite state machines by decomposition and the principal lattice of partitions of a submodular function von Desai, M.P, Narayanan, H, Patkar, Sachin B

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AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs von Sahasrabuddhe, S.D., Raja, H., Arya, K., Desai, M.P.

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Fast DC analysis and its application to combinatorial optimization problems von Trivedi, G., Desai, M.P., Narayanan, H.

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Interconnect delay minimization using a novel pre-mid-post buffer strategy von Prasad, V., Desai, M.P.

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Detailed analysis of FIBL in MOS transistors with high-k gate dielectrics von Mohapatra, N.R., Desai, M.P., Rao, V.R.

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Sub-100 nm CMOS circuit performance with high- K gate dielectrics von Mohapatra, N.R., Dutta, A., Sridhar, G., Desai, M.P., Rao, V.R.

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Inductance characterization of small interconnects using test-signal method von Shah, J.T., Desai, M.P., Sanyal, S.

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An on-chip coupling capacitance measurement technique von Nair, P.A., Gupta, A., Desai, M.P.

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Decomposition of finite state machines for area, delay minimization von Shelar, R.S., Desai, M.P., Narayanan, H.

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On the convergence of block relaxation methods for circuit simulation von Desai, M.P., Hajj, I.N.

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