An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches von Chang, L., Montoye, R.K., Nakamura, Y., Batson, K.A., Eickemeyer, R.J., Dennard, R.H., Haensch, W., Jamsek, D.

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Practical Strategies for Power-Efficient Computing Technologies von Chang, Leland, Frank, David J., Montoye, Robert K., Koester, Steven J., Ji, Brian L., Coteus, Paul W., Dennard, Robert H., Haensch, Wilfried

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A novel dynamic memory cell with internal voltage gain von Luk, W.K., Dennard, R.H.

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A Quarterback's Passion and Desire to Win [People] von Dennard, Robert H.

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How we made DRAM von Dennard, Robert H.

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Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions von Dennard, R.H., Gaensslen, F.H., Hwa-Nien Yu, Rideout, V.L., Bassous, E., Leblanc, A.R.

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Device scaling limits of Si MOSFETs and their application dependencies von Frank, D.J., Dennard, R.H., Nowak, E., Solomon, P.M., Taur, Y., Hon-Sum Philip Wong

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Creativity in the 2000s and Beyond von Dennard, Robert H.

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A perspective on today’s scaling challenges and possible future directions von Dennard, Robert H., Cai, Jin, Kumar, Arvind

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Stable SRAM cell design for the 32 nm node and beyond von Chang, L., Fried, D.M., Hergenrother, J., Sleight, J.W., Dennard, R.H., Montoye, R.K., Sekaric, L., McNab, S.J., Topol, A.W., Adams, C.D., Guarini, K.W., Haensch, W.

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When are transmission-line effects important for on-chip interconnections? von Deutsch, A., Kopcsay, G.V., Restle, P.J., Smith, H.H., Katopis, G., Becker, W.D., Coteus, P.W., Surovic, C.W., Rubin, B.J., Dunne, R.P., Gallo, T., Jenkins, K.A., Terman, L.M., Dennard, R.H., Sai-Halasz, G.A., Krauter, B.L., Knebel, D.R.

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CMOS scaling for high performance and low power-the next ten years von Davari, B., Dennard, R.H., Shahidi, G.G.

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Gated-diode amplifiers von Luk, W.K., Dennard, R.H.

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Revisiting "Evolution of the MOSFET Dynamic RAM - A Personal View" von Dennard, Robert H.

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Practical Strategies for Power-Efficient Computing Technologies : CIRCUIT TECHNOLOGY FOR ULTRA-LOW POWER (ULP) von CHANG, Leland, FRANK, David J, MONTOYE, Robert K, KOESTER, Steven J, JI, Brian L, COTEUS, Paul W, DENNARD, Robert H, HAENSCH, Wilfried

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FDSOI CMOS with dual backgate control for performance and power modulation von Jeng-Bang Yau, Jin Cai, Shi, L., Dennard, R.H., Kumar, A., Sactlger, K.L., Reznicek, A., Solomon, P.M., Qiging Ouyang, Koester, S., Haensch, W.E.

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Past Progress and Future Challenges in LSI Technology: From DRAM and Scaling to Ultra-Low-Power CMOS von Dennard, Robert H.

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Design of ion-implanted MOSFET's with very small physical dimensions von DENNARD, ROBERT H., GAENSSLEN, FRITZ H., YU, HWA-NIEN, LEO RIDEOVT, V., BASSOUS, ERNEST, LEBLANC, ANDRE R.

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Generalized scaling theory and its application to a 1/4 micrometer MOSFET design von Baccarani, G, Wordeman, M R, Dennard, R H

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Structure and method for improving access resistance in U-channel ETSOI von Dennard, Robert H, Joshi, Rajiv V, Williams, Richard Q

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