Device scaling limits of Si MOSFETs and their application dependencies von Frank, D.J., Dennard, R.H., Nowak, E., Solomon, P.M., Taur, Y., Hon-Sum Philip Wong

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An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches von Chang, L., Montoye, R.K., Nakamura, Y., Batson, K.A., Eickemeyer, R.J., Dennard, R.H., Haensch, W., Jamsek, D.

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When are transmission-line effects important for on-chip interconnections? von Deutsch, A., Kopcsay, G.V., Restle, P.J., Smith, H.H., Katopis, G., Becker, W.D., Coteus, P.W., Surovic, C.W., Rubin, B.J., Dunne, R.P., Gallo, T., Jenkins, K.A., Terman, L.M., Dennard, R.H., Sai-Halasz, G.A., Krauter, B.L., Knebel, D.R.

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A novel dynamic memory cell with internal voltage gain von Luk, W.K., Dennard, R.H.

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Gated-diode amplifiers von Luk, W.K., Dennard, R.H.

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Transient pass-transistor leakage current in SOI MOSFET's von Assaderaghi, F., Shahidi, G.G., Wagner, L., Hsieh, M., Pelella, M., Chu, S., Dennard, R.H., Davari, B.

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A room temperature 0.1 μm CMOS on SOI von SHAHIDI, G. G, ANDERSON, C. A, NING, T. H, POLCARI, M. R, WARNOCK, J. D, CHAPPELL, B. A, CHAPPELL, T. I, COMFORT, J. H, DAVARI, B, DENNARD, R. H, FRANCH, R. L, MCFARLAND, P. A, NEELY, J. S

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Submicrometer-channel CMOS for low-temperature operation von Sun, J.Y.-C., Yuan Taur, Dennard, R.H., Klepner, S.P.

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Design and characterization of a CMOS off-chip driver/receiver with reduced power-supply disturbance von Hanafi, H.I., Dennard, R.H., Chen, C.-L., Weiss, R.J., Zicherman, D.S.

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Generalized scaling theory and its application to a 1/4 micrometer MOSFET design von Baccarani, G, Wordeman, M R, Dennard, R H

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Stable SRAM cell design for the 32 nm node and beyond von Chang, L., Fried, D.M., Hergenrother, J., Sleight, J.W., Dennard, R.H., Montoye, R.K., Sekaric, L., McNab, S.J., Topol, A.W., Adams, C.D., Guarini, K.W., Haensch, W.

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Iddq test: sensitivity analysis of scaling von Williams, T.W., Dennard, R.H., Kapur, R., Mercer, M.R., Maly, M.

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High-performance Si1−xGex channel on insulator trigate PFETs featuring an implant-free process and aggressively-scaled fin and gate dimensions von Hashemi, P., Kobayashi, M., Majumdar, A., Yang, L. A., Baraskar, A., Balakrishnan, K., Kim, W., Chan, K., Engelmann, S. U., Ott, J. A., Bedell, S. W., Murray, C. E., Liang, S., Dennard, R. H., Sleight, J. W., Leobandung, E., Park, D.-G

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A fully scaled submicrometer NMOS technology using direct-write E-beam lithography von Wordeman, M.R., Schweighart, A.M., Dennard, R.H., Sai-Halasz, G., Molzen, W.W.

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Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions von Dennard, R.H., Gaensslen, F.H., Hwa-Nien Yu, Rideout, V.L., Bassous, E., Leblanc, A.R.

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Design and experimental technology for 0.1-μm gate-length low-temperature operation FET's von SAI-HALASZ, G. A, WORDEMAN, M. R, CHANG, T. H. P, DENNARD, R. H, KERN, D. P, GANIN, E, RISHTON, S, ZICHERMAN, D. S, SCHMID, H, POLCARI, M. R, NG, H. Y, RESTLE, P. J

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A 4-Mb low-temperature DRAM von Henkels, W.H., Wen, D.-S., Mohler, R.L., Franch, R.L., Bucelot, T.J., Long, C.W., Bracchitta, J.A., Cote, W.J., Bronner, G.B., Taur, Y., Dennard, R.H.

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Evolution of the MOSFET dynamic RAM-A personal view von Dennard, R.H.

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Design of micron MOS switching devices von Dennard, R. H., Gaensslen, F. H., Kuhn, L., Yu, H. N.

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FDSOI CMOS with dielectrically-isolated back gates and 30nm LG high-γ/metal gate von Khater, M, Cai, J, Dennard, R H, Yau, J, Wang, C, Shi, L, Guillorn, M, Ott, J, Ouyang, Q, Haensch, W

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