FPGA-Centric Design Process for Avionic Simulation and Test von Ben Atitallah, Rabie, Viswanathan, Venkatasubramanian, Belanger, Nicolas, Dekeyser, Jean-Luc

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Expressing embedded systems configurations at high abstraction levels with UML MARTE profile: Advantages, limitations and alternatives von Quadri, Imran Rafiq, Gamatié, Abdoulaye, Boulet, Pierre, Meftali, Samy, Dekeyser, Jean-Luc

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SCAC: Weakly-coupled execution model for massively parallel systems von Krichene, Hana, Baklouti, Mouna, Marquet, Philippe, Dekeyser, Jean-Luc, Abid, Mohamed

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Decentralized control for dynamically reconfigurable FPGA systems von Trabelsi, Chiraz, Meftali, Samy, Dekeyser, Jean-Luc

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An MDE Approach for Automatic Code Generation from UML/MARTE to OpenCL von Rodrigues, A. Wendell O., Guyomarc'h, Frederic, Dekeyser, Jean-Luc

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A Model-Driven Approach for Hybrid Power Estimation in Embedded Systems Design von Trabelsi, Chiraz, Ben Atitallah, Rabie, Meftali, Samy, Dekeyser, Jean-Luc, Jemai, Abderrazek

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Towards an automation of the mutation analysis dedicated to model transformation von Aranega, Vincent, Mottu, Jean-Marie, Etien, Anne, Degueule, Thomas, Baudry, Benoit, Dekeyser, Jean-Luc

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Adaptivity in high-performance embedded systems: a reactive control model for reliable and flexible design von Yu, Huafeng, Gamatié, Abdoulaye, Rutten, Éric, Dekeyser, Jean-Luc

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A fast MPSoC virtual prototyping for intensive signal processing applications von Ben Atitallah, Rabie, Piel, Éric, Niar, Smail, Marquet, Philippe, Dekeyser, Jean-Luc

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System level modeling methodology of NoC design from UML-MARTE to VHDL von Elhaji, Majdi, Boulet, Pierre, Zitouni, Abdelkrim, Meftali, Samy, Dekeyser, Jean-Luc, Tourki, Rached

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A low-power oriented architecture for H.264 variable block size motion estimation based on a resource sharing scheme von Elhaji, Majdi, Zitouni, Abdelkrim, Meftali, Samy, Dekeyser, Jean-Luc, Tourki, Rached

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Abstract Clock-Based Design of a JPEG Encoder von Abdallah, A., Gamatie, A., Ben Atitallah, Rabie, Dekeyser, J-L

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ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures von Fakhfakh, Nizar, Ait El Cadi, Abdessamad, Ben Atitallah, Rabie, Ali, Karim M. A., Dekeyser, Jean-Luc

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FPGA-based many-core System-on-Chip design von Baklouti, M., Marquet, Ph, Dekeyser, J.L., Abid, M.

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High level modeling of Dynamic Reconfigurable FPGAs von Quadri, Imran Rafiq, Meftali, Samy, Dekeyser, Jean-Luc

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Data-parallel load balancing strategies von Fonlupt, Cyril, Marquet, Philippe, Dekeyser, Jean-Luc

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Synchronous Modeling and Analysis of Data Intensive Applications von Gamatié, Abdoulaye, Rutten, Éric, Yu, Huafeng, Boulet, Pierre, Dekeyser, Jean-Luc

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Safe design of high-performance embedded systems in an MDE framework von Yu, Huafeng, Gamatié, Abdoulaye, Rutten, Éric, Dekeyser, Jean-Luc

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End of dose interval symptoms in patients treated with natalizumab: A role for serum cytokines? von Cathérine, Dekeyser, Annelien, De Pue, Anne, Sieben, Luc, Algoed, Liesbeth, Van Hijfte, Gerlo, Sarah, Guy, Laureys

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A Model-Driven Design Framework for Massively Parallel Embedded Systems von Gamatié, Abdoulaye, Le Beux, Sébastien, Piel, Éric, Ben Atitallah, Rabie, Etien, Anne, Marquet, Philippe, Dekeyser, Jean-Luc

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