A combined OFDM/SDMA approach von Vandenameele, P., Van Der Perre, L., Engels, M.G.E., Gyselinckx, B., De Man, H.J.

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Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification von van Heijningen, M., Badaroglu, M., Donnay, S., Gielen, G.G.E., De Man, H.J.

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Evolution of substrate noise generation mechanisms with CMOS technology scaling von Badaroglu, M., Wambacq, P., Van der Plas, G., Donnay, S., Gielen, G.G.E., De Man, H.J.

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Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits von Badaroglu, M., van Heijningen, M., Gravot, V., Compiet, J., Donnay, S., Gielen, G.G.E., De Man, H.J.

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Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies von Badaroglu, M., Donnay, S., De Man, H.J., Zinzius, Y.A., Gielen, G.G.E., Sansen, W., Fonden, T., Signell, S.

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SWAN: high-level simulation methodology for digital substrate noise generation von Badaroglu, M., Van der Plas, G., Wambacq, P., Donnay, S., Gielen, G.G.E., De Man, H.J.

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Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate von Badaroglu, M., Van der Plas, G., Wambacq, P., Balasubramanian, L., Tiri, K., Verbauwhede, I., Donnay, S., Gielen, G.G.E., De Man, H.J.

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Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding von Badaroglu, M., Tiri, K., Van der Plas, G., Wambacq, P., Verbauwhede, I., Donnay, S., Gielen, G.G.E., De Man, H.J.

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Design technology research and education for deep-submicron systems of the next century von de Man, H.J.

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Digital ground bounce reduction by supply current shaping and clock frequency Modulation von Badaroglu, M., Wambacq, P., Van der Plas, G., Donnay, S., Gielen, G.G.E., De Man, H.J.

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Optimized synthesis of asynchronous control circuits from graph-theoretic specifications von Vanbekbergen, P., Goossens, G., Catthoor, F., De Man, H.J.

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Formalized methodology for data reuse: exploration for low-power hierarchical memory mappings von Wuytack, S., Diguet, J.-P., Catthoor, F.V.M., De Man, H.J.

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Minimizing the required memory bandwidth in VLSI system realizations von Wuytack, S., Catthoor, F., De Jong, G., De Man, H.J.

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Hardware/software co-design of digital telecommunication systems von Bolsens, I., De Man, H.J., Lin, B., Van Rompaey, K., Vercauteren, S., Verkest, D.

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Digital ground bounce reduction by supply current shaping and clock frequency Modulation von Badaroglu, M, Wambacq, P, Van der Plas, G, Donnay, S, Gielen, G G E, De Man, H J

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The use of threshold functions and Boolean-controlled network elements for macromodeling of LSI circuits von Arnout, G., De Man, H.J.

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High-level address optimization and synthesis techniques for data-transfer-intensive applications von Miranda, M.A., Catthoor, F.V.M., Janssen, M., De Man, H.J.

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Efficient system-level functional verification methodology for multimedia applications von Cupak, M., Catthoor, F., De Man, H.J.

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Practical implementation of a general computer aided design technique for switched capacitor circuits von De Man, H.J., Rabaey, J., Arnout, G., Vandewalle, J.

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Strategy for power-efficient design of parallel systems von Danckaert, K., Masselos, K., Cathoor, F., De Man, H.J., Goutis, C.

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