Call Graph Prefetching for database applications von ANNAVARAM, Murali, PATEL, Jignesh M, DAVIDSON, Edward S

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Active management of data caches by exploiting reuse information von Tam, E.S., Rivers, J.A., Srinivasan, V., Tyson, G.S., Davidson, E.S.

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Data prefetching by dependence graph precomputation von Annavaram, Murali, Patel, Jignesh M., Davidson, Edward S.

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On high-bandwidth data cache design for multi-issue processors von Rivers, J.A., Tyson, G.S., Davidson, E.S., Austin, T.M.

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TAXI: Trace Analysis for x86 Interpretation von Vlaovic, S., Davidson, E.S.

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Register allocation for predicated code von Eichenberger, A.E., Davidson, E.S.

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New method of solution of the traveling salesman problem / by Edward S. Davidson : Report (University of Illinois at Urbana-Champaign. Dept. of Computer Science) no. 201 von Davidson, Edward S

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Improving BTB performance in the presence of DLLs von Vlaovic, S., Davidson, E.S., Tyson, G.S.

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Register queues: a new hardware/software approach to efficient software pipelining von Smelyanskiy, M., Tyson, G.S., Davidson, E.S.

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Parallel Supercomputing Today and the Cedar Approach von Kuck, David J., Davidson, Edward S., Lawrie, Duncan H., Sameh, Ahmed H.

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A Novel Flow-Perfusion Bioreactor Supports 3D Dynamic Cell Culture von Allori, Alexander C., Sailon, Alexander M., Davidson, Edward H., Reformat, Derek D., Allen, Robert J., Warren, Stephen M.

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Minimizing register requirements of a modulo schedule via optimum stage scheduling von EICHENBERGER, A. E, DAVIDSON, E. S, ABRAHAM, S. G

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Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability von Chuan-Hua Chang, Davidson, E.S., Sakallah, K.A.

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A prefetch taxonomy von Viji Srinivasan, Davidson, E.S., Tyson, G.S.

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Approaching a machine-application bound in delivered performance on scientific code von Mangione-Smith, W.H., Shih, T.-P., Abraham, S.G., Davidson, E.S.

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Data prefetching by dependence graph precomputation von Annavaram, M., Patel, J.M., Davidson, E.S.

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Probabilistic Predicate-Aware Modulo Scheduling von Smelyanskiy, Mikhail, Mahlke, Scott, Davidson, Edward S.

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Minimum register requirements for a modulo schedule von Eichenberger, Alexandre E., Davidson, Edward S., Abraham, Santosh G.

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Efficient formulation for optimal modulo schedulers von Eichenberger, Alexandre E., Davidson, Edward S.

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Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining von Smelyanskiy, Mikhail, Tyson, Gary S., Davidson, Edward S.

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