Paradigm shift in ESD qualification von Duvvury, C.

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An Insight Into the ESD Behavior of the Nanometer-Scale Drain-Extended NMOS Device-Part I: Turn-On Behavior of the Parasitic Bipolar von Chatterjee, A, Shrivastava, M, Gossner, H, Pendharkar, S, Brewer, F, Duvvury, C

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An Insight Into ESD Behavior of Nanometer-Scale Drain Extended NMOS (DeNMOS) Devices: Part II (Two-Dimensional Study-Biasing & Comparison With NMOS) von Chatterjee, A, Shrivastava, M, Gossner, H, Pendharkar, S, Brewer, F, Duvvury, C

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Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices von Diaz, C.H., Sung-Mo Kang, Duvvury, C.

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Characterization and Optimization of Sub-32-nm FinFET Devices for ESD Applications von Thijs, S., Tremouilles, D., Russ, C., Griffoni, A., Collaert, N., Rooyackers, R., Linten, D., Scholz, M., Duvvury, C., Gossner, H., Jurczak, M., Groeseneken, G.

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Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors von Kwang-Hoon Oh, Duvvury, C., Banerjee, K., Dutton, R.W.

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Modeling the 3D self ballasting behavior and filamentation under high current stressing in DeNMOS von Chatterjee, A., Pendharkar, S., Duvvury, C., Brewer, F.

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Drain Extended NMOS High Current Behavior and ESD Protection Strategy for HV Applications in Sub-100nm CMOS Technologies von Boselli, G., Vassilev, V., Duvvury, C.

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A guide to short-channel effects in MOSFETs von Duvvury, Charvaka

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Robust high current ESD performance of nano-meter scale DeNMOS by source ballasting von Chatterjee, A, Brewer, F, Gossner, H, Pendharkar, S, Duvvury, C

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Improving surface bipolar activity in thin gate oxide DE-NMOS - A critical HV I/O protection element for nano-meter scale technologies von Chatterjee, A, Pendharkar, S, Gossner, H, Duvvury, C, Brewer, F

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ESD: a pervasive reliability concern for IC technologies von Duvvury, C., Amerasekera, A.

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ESD qualification changes for 45nm and beyond von Duvvury, C.

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Latch-up in 65nm CMOS technology: a scaling perspective von Boselli, G., Reddy, V., Duvvury, C.

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3D device modeling of damage due to filamentation under an ESD event in nanometer scale drain extended NMOS (DE-NMOS) von Chatterjee, A., Pendharkar, S., Gossner, H., Duvvury, C., Banerjee, K.

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A.1 ESD protection targets von Duvvury, Charvaka

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Gate oxide failures due to anomalous stress from HBM ESD testers von Duvvury, Charvaka, Steinhoff, Robert, Boselli, Gianluca, Reddy, Vijay, Kunz, Hans, Marum, Steve, Cline, Roger

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An Insight into the High Current ESD Behavior of Drain Extended NMOS (DENMOS) Devices in Nanometer Scale CMOS Technologies von Chatterjee, Amitabh, Pendharkar, Sameer, Lin, Yen-Yi, Duvvury, Charvaka, Banerjee, Kaustav

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Latchup in voltage tolerant circuits: a new phenomenon von Salcedo-Suñer, Jorge, Duvvury, Charvaka, Cline, Roger, Cadena-Hernandez, Alfonso

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System and Method for Efficient Electrostatic Discharge Testing and Analysis von Hussain Amjad, Loshakov Svetlana, Duvvury Charvaka

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