Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits von Dreslinski, Ronald G., Wieckowski, Michael, Blaauw, David, Sylvester, Dennis, Mudge, Trevor

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Rethinking DRAM's Page Mode With STT-MRAM von Oh, Byoungchan, Abeyratne, Nilmini, Kim, Nam Sung, Ahn, Jeongseob, Dreslinski, Ronald G., Mudge, Trevor

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Energy-Autonomous Wireless Communication for Millimeter-Scale Internet-of-Things Sensor Nodes von Chen, Yajing, Chiotellis, Nikolaos, Chuo, Li-Xuan, Pfeiffer, Carl, Shi, Yao, Dreslinski, Ronald G., Grbic, Anthony, Mudge, Trevor, Wentzloff, David D., Blaauw, David, Kim, Hun Seok

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The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips von Davidson, Scott, Xie, Shaolin, Torng, Christopher, Al-Hawai, Khalid, Rovinski, Austin, Ajayi, Tutu, Vega, Luis, Zhao, Chun, Zhao, Ritchie, Dai, Steve, Amarnath, Aporva, Veluri, Bandhav, Gao, Paul, Rao, Anuj, Liu, Gai, Gupta, Rajesh K., Zhang, Zhiru, Dreslinski, Ronald, Batten, Christopher, Taylor, Michael Bedford

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Finding and Indexing Vehicle Maneuvers From Dashboard Camera Video von Zekany, Stephen A., Larsen, Thomas F., Dreslinski, Ronald G., Wenisch, Thomas F.

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The M5 Simulator: Modeling Networked Systems von Binkert, N.L., Dreslinski, R.G., Hsu, L.R., Lim, K.T., Saidi, A.G., Reinhardt, S.K.

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A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator von Park, Dong-Hyeon, Pal, Subhankar, Feng, Siying, Gao, Paul, Tan, Jielun, Rovinski, Austin, Xie, Shaolin, Zhao, Chun, Amarnath, Aporva, Wesley, Timothy, Beaumont, Jonathan, Chen, Kuan-Yu, Chakrabarti, Chaitali, Taylor, Michael Bedford, Mudge, Trevor, Blaauw, David, Kim, Hun-Seok, Dreslinski, Ronald G.

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Tablext: A combined neural network and heuristic based table extractor von Colter, Zach, Fayazi, Morteza, Youbi, Zineb Benameur-El, Kamp, Serafina, Yu, Shuyan, Dreslinski, Ronald

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Reining in Long Tails in Warehouse-Scale Computers with Quick Voltage Boosting Using Adrenaline von Hsu, Chang-Hong, Zhang, Yunqi, Laurenzano, Michael A., Meisner, David, Wenisch, Thomas, Dreslinski, Ronald G., Mars, Jason, Tang, Lingjia

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Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS von Fick, D., Dreslinski, R. G., Giridhar, B., Gyouho Kim, Sangwon Seo, Fojtik, M., Satpathy, S., Yoonmyung Lee, Daeyeon Kim, Liu, Nurrachman, Wieckowski, M., Chen, G., Mudge, T., Blaauw, D., Sylvester, D.

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Exploring Fine-Grained Heterogeneity with Composite Cores von Lukefahr, Andrew, Padmanabha, Shruti, Das, Reetuparna, Sleiman, Faissal M., Dreslinski, Ronald G., Wenisch, Thomas F., Mahlke, Scott

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Designing Future Warehouse-Scale Computers for Sirius, an End-to-End Voice and Vision Personal Assistant von Hauswald, Johann, Laurenzano, Michael A, Zhang, Yunqi, Yang, Hailong, Kang, Yiping, Li, Cheng, Rovinski, Austin, Khurana, Arjun, Dreslinski, Ronald G, Mudge, Trevor, Petrucci, Vinicius, Tang, Lingjia, Mars, Jason

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Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor With Synthesizable PLL von Rovinski, Austin, Veluri, Bandhav, Rao, Anuj, Ajayi, Tutu, Puscar, Julian, Dai, Steve, Zhao, Ritchie, Richmond, Dustin, Zhang, Zhiru, Galton, Ian, Batten, Christopher, Zhao, Chun, Taylor, Michael B., Dreslinski, Ronald G., Al-Hawaj, Khalid, Gao, Paul, Xie, Shaolin, Torng, Christopher, Davidson, Scott, Amarnath, Aporva, Vega, Luis

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Applications of Artificial Intelligence on the Modeling and Optimization for Analog and Mixed-Signal Circuits: A Review von Fayazi, Morteza, Colter, Zachary, Afshari, Ehsan, Dreslinski, Ronald

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MBus: A System Integration Bus for the Modular Microscale Computing Class von Pannuto, Pat, Yoonmyung Lee, Ye-Sheng Kuo, ZhiYoong Foo, Kempke, Benjamin, Gyouho Kim, Dreslinski, Ronald G., Blaauw, David, Dutta, Prabal

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Centip3De: A 64-Core, 3D Stacked Near-Threshold System von Dreslinski, R. G., Fick, D., Giridhar, B., Gyouho Kim, Sangwon Seo, Fojtik, M., Satpathy, S., Yoonmyung Lee, Daeyeon Kim, Liu, N., Wieckowski, M., Chen, G., Sylvester, D., Blaauw, D., Mudge, T.

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Sirius Implications for Future Warehouse-Scale Computers von Hauswald, Johann, Laurenzano, Michael A., Yunqi Zhang, Cheng Li, Rovinski, Austin, Khurana, Arjun, Dreslinski, Ronald G., Mudge, Trevor, Petrucci, Vinicius, Lingjia Tang, Mars, Jason

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AnGeL: Fully-Automated Analog Circuit Generator Using a Neural Network Assisted Semi-Supervised Learning Approach von Fayazi, Morteza, Taba, Morteza Tavakoli, Afshari, Ehsan, Dreslinski, Ronald

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Demystifying Graph Sparsification Algorithms in Graph Properties Preservation von Chen, Yuhan, Ye, Haojie, Vedula, Sanketh, Bronstein, Alex, Dreslinski, Ronald, Mudge, Trevor, Talati, Nishil

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DAP: A 507-GMACs/J 256-Core Domain Adaptive Processor for Wireless Communication and Linear Algebra Kernels in 12-nm FINFET von Chen, Kuan-Yu, Yang, Chi-Sheng, Sun, Yu-Hsiu, Tseng, Chien-Wei, Fayazi, Morteza, He, Xin, Feng, Siying, Yue, Yufan, Mudge, Trevor, Dreslinski, Ronald, Kim, Hun-Seok, Blaauw, David

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