Blurring the Lines between Memory and Computation von Das, Reetuparna

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nPoRe: n-polymer realigner for improved pileup-based variant calling von Dunn, Tim, Blaauw, David, Das, Reetuparna, Narayanasamy, Satish

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Special Issue on In-Memory Computing von Das, Reetuparna

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Ultra-rapid somatic variant detection via real-time targeted amplicon sequencing von Wadden, Jack, Newell, Brandon S., Bugbee, Joshua, John, Vishal, Bruzek, Amy K., Dickson, Robert P., Koschmann, Carl, Blaauw, David, Narayanasamy, Satish, Das, Reetuparna

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A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing von Wang, Jingcheng, Wang, Xiaowei, Eckert, Charles, Subramaniyan, Arun, Das, Reetuparna, Blaauw, David, Sylvester, Dennis

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Systems Challenges and Opportunities for Genomics von Das, Reetuparna, Narayanasamy, Satish, Jones, Timothy, Mullins, Robert

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A case for dynamic frequency tuning in on-chip networks von Mishra, Asit K., Das, Reetuparna, Eachempati, Soumya, Iyer, Ravi, Vijaykrishnan, N., Das, Chita R.

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Performance and power optimization through data compression in Network-on-Chip architectures von Das, R., Mishra, A.K., Nicopoulos, C., Dongkook Park, Narayanan, V., Iyer, R., Yousif, M.S., Das, C.R.

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Hardware-friendly User-specific Machine Learning for Edge Devices von Goyal, Vidushi, Das, Reetuparna, Bertacco, Valeria

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Eidetic: An In-Memory Matrix Multiplication Accelerator for Neural Networks von Eckert, Charles, Subramaniyan, Arun, Wang, Xiaowei, Augustine, Charles, Iyer, Ravishankar, Das, Reetuparna

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BitSET: Bit-Serial Early Termination for Computation Reduction in Convolutional Neural Networks von Pan, Yunjie, Yu, Jiecao, Lukefahr, Andrew, Das, Reetuparna, Mahlke, Scott

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Power-aware NoCs through routing and topology reconfiguration von Parikh, Ritesh, Das, Reetuparna, Bertacco, Valeria

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TF-Net: Deploying Sub-Byte Deep Neural Networks on Microcontrollers von Yu, Jiecao, Lukefahr, Andrew, Das, Reetuparna, Mahlke, Scott

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Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks von Eckert, Charles, Wang, Xiaowei, Wang, Jingcheng, Subramaniyan, Arun, Sylvester, Dennis, Blaauw, David, Das, Reetuparna, Iyer, Ravi

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A 2.46M Reads/s Seed-Extension Accelerator for Next-Generation Sequencing Using a String-Independent PE Array von Wang, Zhehong, Zhang, Tianjun, Fujiki, Daichi, Subramaniyan, Arun, Wu, Xiao, Yasuda, Makoto, Miyoshi, Satoru, Kawaminami, Masaru, Das, Reetuparna, Narayanasamy, Satish, Blaauw, David

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Application-to-core mapping policies to reduce memory system interference in multi-core systems von Das, R., Ausavarungnirun, R., Mutlu, O., Kumar, A., Azimi, M.

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A High-Throughput Pruning-Based Pair-Hidden-Markov-Model Hardware Accelerator for Next-Generation DNA Sequencing von Wu, Xiao, Subramaniyan, Arun, Wang, Zhehong, Narayanasamy, Satish, Das, Reetuparna, Blaauw, David

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Application-aware prioritization mechanisms for on-chip networks von Das, Reetuparna, Mutlu, Onur, Moscibroda, Thomas, Das, Chita R.

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A case for hierarchical rings with deflection routing: An energy-efficient on-chip communication substrate von Ausavarungnirun, Rachata, Fallin, Chris, Yu, Xiangyao, Chang, Kevin Kai-Wei, Nazario, Greg, Das, Reetuparna, Loh, Gabriel H., Mutlu, Onur

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In-Memory Data Parallel Processor von Fujiki, Daichi, Mahlke, Scott, Das, Reetuparna

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