Roadmap Differentiation and Emerging Trends in BCD Technology von Contiero, C., Andreini, A., Galbiati, P.

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Automatic 2-D and 3-D simulation of parasitic structures in smart-power integrated circuits von Gnani, E., Giudicissi, V., Vissarion, R., Contiero, C., Rudan, M.

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Overstress and electrostatic discharge in CMOS and BCD integrated circuits von Meneghesso, G., Ciappa, M., Malberti, P., Sponton, L., Croce, G., Contiero, C., Zanoni, E.

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0.18 μm BCD -High Voltage Gate (HVG) Process to address Advanced Display Drivers Roadmap von Annese, M., Bertaiola, S., Croce, G., Milani, A., Roggero, R., Galbiati, P., Contiero, C.

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ESD protection structures for BCD5 smart power technologies von Sponton, L., Cerati, L., Croce, G., Chrappan, F., Contiero, C., Meneghesso, G., Zanoni, E.

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Smart power technologies evolution von Murari, B., Contiero, C., Gariboldi, R., Sueri, S., Russo, A.

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Hot-electron-induced degradation in high-voltage submicron DMOS transistors von Manzini, S., Contiero, C.

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Smart power approaches VLSI complexity von Contiero, C., Galbiati, P., Palmieri, M., Ricotti, G., Stella, R.

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HBM and TLP ESD robustness in smart-power protection structures von Santirosia, S., Meneghesso, G., Novarini, E., Contieroa, C., Zanoni, E.

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A new integrated silicon gate technology combining bipolar linear, CMOS logic, and DMOS power parts von Andreini, A., Contiero, C., Galbiati, P.

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Hot-electron injection and trapping in the gate oxide of submicron DMOS transistors von Manzini, S., Gallerano, A., Contiero, C.

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ACTIVATION OF THE TNF-Α SIGNALING PATHWAY THROUGH THE TNFR2 RECEPTOR AND ANTI-APOPTOTIC GENES IN GASTRIC CANCER von Rossi, AFT, Contiero, JC, Silva, AE

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High doped drain double-Resurf 100V P-channel MOS on SOI 0.35 μm BCD technology von Palumbo, V., Venturato, M., Gallo, M., Pozzobon, F., Galbiati, M.P., Contiero, C.

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HVCMOS8A: 22V-42V Rated MOS integration in a 0.18μm technology platform for High Voltage applications von Bach, S., Atzeni, L., Molfese, A., Dundulachi, A., Castellana, E., Croce, G., Contiero, C.

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BCD8 from 7V to 70V: a new 0.l8μm Technology Platform to Address the Evolution of Applications towards Smart Power ICs with High Logic Contents von Riccardi, D., Causio, A., Filippi, I., Paleari, A., Pregnolato, L.V.A., Galbiati, P., Contiero, C.

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Hot-carrier reliability in submicrometer LDMOS transistors von Versari, R., Pieracci, A., Manzini, S., Contiero, C., Ricco, B.

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20V-40V Symmetrical Vertical Trench nMOS (SVT MOS) design for display driver ICs von Annese, M., Montanmi, P., Toia, F., Zullino, L., Contiero, C.

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Extraction of channel doping profile in DMOS transistors von Pieracci, A., Lanzoni, M., Galbiati, P., Manzini, S., Contiero, C., Ricco, B.

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LDMOS implementation in a 0.35 /spl mu/m BCD technology (BCD6) von Moscatelli, A., Merlini, A., Croce, G., Galbiati, P., Contiero, C.

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Progress in power ICs and MEMS, "analog" technologies to interface the real world von CONTIERO, Claudio, MURARI, Bnmo, VIGNA, Benedetto

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